公开(公告)号：US20080227257A1

公开(公告)日：2008-09-18

申请号：US11856514

申请日：2007-09-17

申请人： Ming-Teng Hsieh

发明人： Ming-Teng Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L27/10823 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66621 ,  H01L29/78

摘要： A method for forming a semiconductor device comprises providing a substrate. A N type region and a non-N type region are formed in the substrate. The substrate is wet etched to form a protruding portion in the N type region and a concave portion in the non-N type region. A gate structure is formed in the concave portion and insulating spacers are formed on sidewalls of the protruding portion.

摘要翻译： 一种用于形成半导体器件的方法包括提供衬底。 在基板上形成N型区域和非N型区域。 对衬底进行湿式蚀刻以在N型区域中形成突出部分，在非N型区域形成凹部。 在该凹部形成有栅极结构，在突出部的侧壁上形成绝缘隔板。

公开(公告)号：US20120288968A1

公开(公告)日：2012-11-15

申请号：US13106837

申请日：2011-05-12

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for repairing a semiconductor structure having a current-leakage issue includes finding a semiconductor structure having a current-leakage issue through application of a test voltage from an electric test device and applying an electric power stress to the semiconductor structure to melt a stringer or a bridge between two conductive elements or to allow the stringer or the bridge to be oxidized.

摘要翻译： 一种用于修复具有电流泄漏问题的半导体结构的方法包括通过施加来自电测试装置的测试电压来发现具有电流泄漏问题的半导体结构，并向半导体结构施加电力应力以熔化桁条或 两个导电元件之间的桥梁或允许桁条或桥被氧化。

公开(公告)号：US20120288967A1

公开(公告)日：2012-11-15

申请号：US13105909

申请日：2011-05-12

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/30 ,  H01L21/306

CPC分类号： H01L21/56 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for decapsulating an integrated circuit package without the need of using a mask during the decapsulation process is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided. The caustic solution is capable of etching the molding compound and intermittently contacts a pre-selected area of the molding compound to etch the molding compound. As a consequence, the caustic solution removes the molding compound in the pre-selected area so the circuit element in the package is substantially exposed.

摘要翻译： 公开了一种在解封装过程中不需要使用掩模的集成电路封装的封装方法。 首先，提供一个包装。 封装件至少包括电路元件和封装电路的模塑料。 其次，同时提供苛性碱溶液。 苛性溶液能够蚀刻模塑料并间歇地接触模塑料的预先选择的区域以蚀刻模塑料。 因此，苛性溶液去除了预选区域中的模塑料，使得包装中的电路元件基本上暴露出来。

公开(公告)号：US20120288684A1

公开(公告)日：2012-11-15

申请号：US13106841

申请日：2011-05-12

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B32B3/00 ,  B23K1/20 ,  B23K31/02

CPC分类号： H01L24/85 ,  H01L23/3121 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/1134 ,  H01L2224/13019 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/81191 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  Y10T428/24612 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/4554

摘要： A bump structure including a base portion, an inlaid wire segment, and a protruding tail segment is provided. The base portion is bonded on a bonding site. The inlaid wire segment is pressed into a top surface of the base portion. The protruding tail segment extends from the inlaid wire segment. The methods for forming the bump structure are also provided.

摘要翻译： 提供了包括基部，镶嵌线段和突出尾段的凸块结构。 基部结合在接合部位上。 嵌入的线段被压入基部的顶表面。 突出的尾部段从嵌入的线段延伸。 还提供了用于形成凸块结构的方法。

公开(公告)号：US20120288966A1

公开(公告)日：2012-11-15

申请号：US13105905

申请日：2011-05-12

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/30 ,  H01L21/306

CPC分类号： H01L21/31133 ,  H01L2224/48091 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for decapsulating an integrated circuit package in the absence of a mask is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided and drained. The caustic solution is capable of etching the molding compound while in continuous contact with the molding compound to etch the molding compound. As a consequence, the molding compound is removed so that the circuit element in the package is substantially exposed.

摘要翻译： 公开了一种在没有掩模的情况下对集成电路封装进行封装的方法。 首先，提供一个包装。 封装件至少包括电路元件和封装电路的模塑料。 第二，同时提供和排出苛性碱溶液。 苛性溶液能够在与模塑料连续接触的同时刻蚀模塑料以蚀刻模塑料。 结果，除去模塑料，使包装中的电路元件基本上露出。

公开(公告)号：US20120288355A1

公开(公告)日：2012-11-15

申请号：US13105881

申请日：2011-05-11

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/677 ,  B65B31/00

CPC分类号： H01L21/67393

摘要： A method for storing wafers is disclosed. A plurality of wafers are placed into the wafer cassette box. The wafer cassette box is hermetically sealed and pumped down to vacuum for the wafer storage. Alternatively, the wafers carried by a holder conveyed on a wafer conveyor are placed into a pump-down chamber enclosing a section of the wafer conveyor. The pump-down chamber is hermetic sealed and pumped down to vacuum for the wafer storage on the wafer conveyor.

摘要翻译： 公开了一种用于存储晶片的方法。 多个晶片被放置在晶片盒盒中。 将晶片盒盒密封并泵送到真空以进行晶片储存。 或者，由在晶片传送器上输送的保持器承载的晶片被放置在包围晶片传送器的一部分的抽空室中。 抽气室被气密密封并泵送到真空以用于在晶片输送机上的晶片储存。

公开(公告)号：US06403418B2

公开(公告)日：2002-06-11

申请号：US09551535

申请日：2000-04-18

申请人： Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Tean-Sen Jen ,  Ming-Teng Hsieh

发明人： Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Tean-Sen Jen ,  Ming-Teng Hsieh

IPC分类号： H01L218242

CPC分类号： H01L28/91 ,  H01L21/3143 ,  H01L21/31604 ,  H01L27/10855

摘要： A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.

摘要翻译： 公开了一种制造高密度动态随机存取存储器（DRAM）单元的杯形圆柱形电容器的方法。 杯状电容器形状通过首先在硅衬底上沉积第一多晶硅层来实现; 然后通过常规的光刻和蚀刻技术形成覆盖第一多晶硅层和限定的第三介电冠的第三介电层; 沉积覆盖第三介电冠和第一多晶硅层的第二多晶硅层; 然后第一多晶硅和第二多晶硅层垂直各向异性回蚀以限定圆柱形电容器的存储节点; 去除第三介质冠; 最后，电容器的电容器电介质层和多晶硅顶板形成为完成用于高密度DRAM应用的杯形圆柱形电容器形成。

公开(公告)号：US5923989A

公开(公告)日：1999-07-13

申请号：US81598

申请日：1998-05-20

申请人： Shian-Jyh Lin ,  Tsu-An Lin ,  Wen-Chieh Chang ,  Shiou-Yu Wang ,  Tean-Sen Jen ,  Hui-Jen Yang ,  Jia-Shyong Cheng ,  Ming-Teng Hsieh

发明人： Shian-Jyh Lin ,  Tsu-An Lin ,  Wen-Chieh Chang ,  Shiou-Yu Wang ,  Tean-Sen Jen ,  Hui-Jen Yang ,  Jia-Shyong Cheng ,  Ming-Teng Hsieh

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/84

摘要： A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and bitlines are formed on a semiconductor silicon substrate. Next, a dielectric layer and a doped polysilicon layer are sequentially deposited over the entire silicon substrate. The dielectric layer and doped polysilicon layer are then partially etched to open source contact windows. Then, a polysilicon layer is deposited overlaying the doped polysilicon layer and filling into the source contact windows. Next, the polysilicon layer and doped polysilicon layers are partially etched to define bottom electrodes of the capacitors. Next, tilt angle implantation is performed to implant impurities into top surface and four sidewalls of the polysilicon layer and doped polysilicon layer. Next, a rugged polysilicon layer is deposited overlaying the polysilicon, doped polysilicon and third dielectric layers. Next, the polysilicon layer is anisotropically etched by using the rugged polysilicon layer as an etching mask to transfer rugged surface profile from the rugged polysilicon layer to the polysilicon layer. Finally, an interelectrode dielectric layer and a third polysilicon layer as top electrodes of the capacitors are sequentially formed to complete the rugged capacitor for high density DRAM applications.

摘要翻译： 公开了一种制造高密度动态随机存取存储器（DRAM）单元的坚固电容器结构的方法。 首先，在半导体硅衬底上形成MOSFET，字线和位线。 接下来，在整个硅衬底上依次沉积介电层和掺杂多晶硅层。 然后将电介质层和掺杂多晶硅层部分地蚀刻到开源接触窗口。 然后，沉积覆盖掺杂多晶硅层并填充到源极接触窗口中的多晶硅层。 接下来，部分蚀刻多晶硅层和掺杂多晶硅层以限定电容器的底部电极。 接下来，进行倾斜角注入以将杂质植入多晶硅层的顶表面和四个侧壁以及掺杂多晶硅层。 接下来，沉积覆盖多晶硅，掺杂多晶硅和第三介电层的坚固的多晶硅层。 接下来，通过使用坚固的多晶硅层作为蚀刻掩模来将多晶硅层各向异性地蚀刻，以将粗糙的表面轮廓从坚固的多晶硅层转移到多晶硅层。 最后，依次形成作为电容器顶电极的电极间电介质层和第三多晶硅层，以完成用于高密度DRAM应用的坚固电容器。

公开(公告)号：US20120289048A1

公开(公告)日：2012-11-15

申请号：US13104986

申请日：2011-05-11

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/306 ,  H01L21/304

CPC分类号： H01L27/0203 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

摘要翻译： 一种用于获得现有集成电路的布局设计的方法，其中集成电路管芯以倾斜角抛光以形成倾斜的抛光表面，并且获得倾斜抛光表面的一个或多个图像。 图像可以直接重叠，或者图像或图像可以用于提供信息以获得包括布局结构的至少一个重复单元结构的布局设计。

公开(公告)号：US08394721B2

公开(公告)日：2013-03-12

申请号：US13104986

申请日：2011-05-11

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/311

CPC分类号： H01L27/0203 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

摘要翻译： 一种用于获得现有集成电路的布局设计的方法，其中集成电路管芯以倾斜角抛光以形成倾斜的抛光表面，并且获得倾斜抛光表面的一个或多个图像。 图像可以直接重叠，或者图像或图像可以用于提供信息以获得包括布局结构的至少一个重复单元结构的布局设计。