-
1.发明授权公开(公告)号：US06788562B2
公开(公告)日：2004-09-07
申请号：US10328435
申请日：2002-12-23
IPC分类号： G11C700
CPC分类号： G11C17/126 , G11C7/18 , G11C16/0475 , G11C16/0491 , H01L27/115
摘要： Disclosed is a device and a method for enabling a programmable semiconductor memory device to provide a block selection transistor of a high voltage withstand type, to prevent the voltage from being decreased at the time of programming, to prevent the readout current from being decreased and to provide a constant sum resistance of the electrically conductive regions without dependency upon the memory cell locations.
摘要翻译： 公开了一种用于使可编程半导体存储器件能够提供高耐压型的块选择晶体管的装置和方法，以防止在编程时电压降低，以防止读出电流减小，并且 提供导电区域的恒定的和电阻，而不依赖于存储器单元位置。
-
2.发明授权公开(公告)号：US06927450B2
公开(公告)日：2005-08-09
申请号：US10387369
申请日：2003-03-12
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11568 , G11C16/0475 , H01L27/105 , H01L27/11573 , H01L29/66833 , H01L29/7923
摘要： A method of manufacturing a semiconductor device include a step of forming an insulating layer, which is obtained by building up a first oxide film, a nitride film and a second oxide film on a substrate in the order mentioned, and a Salicide step of forming a Salicide-structure gate electrode on the insulating film. A silicidation reaction between the substrate surface and an N+ diffusion region is prevented in the Salicide step by causing the insulating layer to remain even in a region on the substrate besides that immediately underlying the gate electrode.
摘要翻译： 制造半导体器件的方法包括以下述顺序在基板上形成第一氧化膜，氮化物膜和第二氧化物膜而形成绝缘层的步骤，以及形成 绝缘膜上的硅化物结构栅电极。 在硅化物步骤中，通过使绝缘层甚至在基板的正下方即使在基板上的区域中保持，从而防止了衬底表面和N +扩散区域之间的硅化反应。
-
公开(公告)号：US5593904A
公开(公告)日：1997-01-14
申请号：US451548
申请日：1995-05-26
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/1126 , H01L27/112
摘要： A plurality of gate electrodes are formed over a semiconductor substrate of a first conductivity type, and impurities of a second conductivity type are introduced into the substrate with a mask of the gate electrodes, to form source/drain impurity regions. Then, an insulating pattern is formed on the gate electrode and the source/drain impurity regions, and impurities of the second conductivity type are introduced into the substrate with a mask of the insulating pattern, to form a deep base region which is connected to one of the source/drain impurity regions. Also, impurities of the first conductivity type are introduced into the substrate with a mask of the insulating pattern, to form a shallow emitter region.
摘要翻译： 在第一导电类型的半导体衬底上形成多个栅电极，并且用栅电极的掩模将第二导电类型的杂质引入到衬底中，以形成源/漏杂质区。 然后，在栅电极和源极/漏极杂质区上形成绝缘图案，并且用绝缘图案的掩模将第二导电类型的杂质引入到衬底中，以形成连接到绝缘图案的深基区 的源极/漏极杂质区域。 此外，第一导电类型的杂质用绝缘图案的掩模引入到衬底中，以形成浅的发射极区域。
-
公开(公告)号：US07039775B2
公开(公告)日：2006-05-02
申请号：US10164657
申请日：2002-06-06
申请人： Kenji Saito , Teiichiro Nishizaka
发明人： Kenji Saito , Teiichiro Nishizaka
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： A non-volatile storage device (1), such as a flash memory, that may include a plurality of sectors and additional sectors has been disclosed. Sectors may include a physical sector number. A logical sector number may be assigned to a sector with additional sectors not assigned a logical sector number. When an erase/write command is executed for a logical sector address, an additional sector may be selected to have the new or updated data written into and may be assigned the logical sector number. The additional sector assigned the logical sector number may then have the new or updated data written into while the physical sector number previously assigned the logical address is being erased. In this way, an apparent erase time may be reduced. The newly erased sector may be a new additional sector. Each sector may include a control data section (101) and a data section (102). Control data section (101) may store control data for controlling erasing and rewriting.
摘要翻译： 已经公开了可以包括多个扇区和附加扇区的诸如闪存的非易失性存储设备（1）。 部门可以包括物理部门号码。 可以将逻辑扇区号分配给具有未分配逻辑扇区号的附加扇区的扇区。 当对逻辑扇区地址执行擦除/写入命令时，可以选择附加扇区以将新的或更新的数据写入并且可以分配逻辑扇区号。 分配逻辑扇区号的附加扇区然后可以在先前分配了逻辑地址的物理扇区号被擦除的同时写入新的或更新的数据。 以这种方式，可以减少表观擦除时间。 新擦除的行业可能是新增的行业。 每个扇区可以包括控制数据部分（101）和数据部分（102）。 控制数据部（101）可以存储用于控制擦除和重写的控制数据。
-
5.发明授权Semiconductor memory device and control method and manufacturing method thereof 失效半导体存储器件及其控制方法及其制造方法公开(公告)号：US06979856B2
公开(公告)日：2005-12-27
申请号：US10648295
申请日：2003-08-27
申请人： Teiichiro Nishizaka , Isami Sakai , Akira Yoshino , Shinichi Kawai , Kiyokazu Ishige , Tomohiro Hamajima , Motoko Tanaka
发明人： Teiichiro Nishizaka , Isami Sakai , Akira Yoshino , Shinichi Kawai , Kiyokazu Ishige , Tomohiro Hamajima , Motoko Tanaka
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/8246 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11568 , G11C16/0416 , H01L27/115
摘要： A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film. The first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines. The second diffusion region is connected to a program and erase bit line.
摘要翻译： 半导体存储器件包括设置在第一和第二扩散区域之间的半导体衬底上的第一绝缘膜，设置在第一绝缘膜上的第一栅电极，设置在第二扩散区和第三扩散区之间的半导体衬底上的第二绝缘膜 以及设置在第二绝缘膜上的第二栅电极。 第一和第二扩散区域，第一绝缘膜和第一栅电极构成第一存储单元，而第二和第三扩散区域，第二绝缘膜和第二栅电极构成第二存储单元。 第一和第二栅电极共同连接形成字线电极。 第一和第三扩散区域连接到第一和第二读取位线。 第二扩散区连接到编程和擦除位线。
-
6.发明授权NAND ROM with transistor strings located at trench bottoms as well as between trenches 失效NAND ROM，其中晶体管串位于沟槽底部以及沟槽之间
公开(公告)号：US5635748A
公开(公告)日：1997-06-03
申请号：US370818
申请日：1995-01-10
申请人： Teiichiro Nishizaka
发明人： Teiichiro Nishizaka
IPC分类号： H01L27/10 , H01L27/112 , H01L29/78
CPC分类号： H01L27/112
摘要： A NAND ROM with an improved integration level is described. A number of trenches are formed in stripe pattern at the surface of a semiconductor substrate, and an insulating film for isolation between devices is formed at the sidewalls, respectively, of each trench. A first unit array consisting of MOSFETs connected in series is arranged in each first active region defined between two adjacent trenches. A second active region is defined in the bottom of each trench and a second unit array is arranged therein. Distinguished from the trench isolation technique which provides trenches between unit arrays, instead, according to the present invention, sidewalls of insulating film are formed. The trench width is limited to the minimum feature size involving the lithography. On the other hand, the width of the insulating-film sidewalls are independent of the limitation, permitting the size of the 64-Mbit mask ROM chip to be about 2 mm smaller.
摘要翻译： 描述了具有改进的集成度的NAND ROM。 在半导体衬底的表面上以条纹图案形成多个沟槽，并且在每个沟槽的侧壁处分别形成用于隔离的绝缘膜。 由串联连接的MOSFET组成的第一单元阵列布置在限定在两个相邻沟槽之间的每个第一有源区中。 第二有源区被限定在每个沟槽的底部，并且第二单元阵列被布置在其中。 与在单元阵列之间提供沟槽的沟槽隔离技术区别在于，根据本发明，形成绝缘膜的侧壁。 沟槽宽度限于涉及光刻的最小特征尺寸。 另一方面，绝缘膜侧壁的宽度与限制无关，允许64-Mbit掩模ROM芯片的尺寸小约2mm。
-
7.发明授权Semiconductor memory having a plurality of memory banks and sub-bit lines which are connected to a main bit line via MOS transistors whose gates are commonly connected to a selection line 失效具有多个存储体和子位线的半导体存储器，其通过其栅极共同连接到选择线的MOS晶体管连接到主位线
公开(公告)号：US5625586A
公开(公告)日：1997-04-29
申请号：US606300
申请日：1996-02-23
CPC分类号： G11C17/126 , G11C11/56 , G11C11/5692 , G11C16/0491 , G11C16/24 , G11C7/18
摘要： In a semiconductor memory comprising one main bit line D1, a pair of main ground lines VG1 and VD2, a plurality of memory cell banks to be selectively connected to the main bit line D1 and the main ground lines VG1 and VD2, and a plurality of word lines W1 to Wn extending through the memory cell banks, each of the memory cell banks includes a plurality of wirings L1, L2, L3, L4 and L5 located in parallel to each other, and a threshold of a block selection transistor BT11 connected between the main bit line D1 and the wiring L3, is lower than that of block selection transistors BT12 and BT13 connected between the main bit line D1 and the wiring L2 and between the main bit line D1 and the wiring L4, respectively.
摘要翻译： 在包括一个主位线D1，一对主地线VG1和VD2的半导体存储器中，选择性地连接到主位线D1和主地线VG1和VD2的多个存储单元组，以及多个 字线W1至Wn延伸穿过存储单元组，每个存储单元组包括彼此并联的多个布线L1，L2，L3，L4和L5，并且块选择晶体管BT11的阈值连接在 主位线D1和布线L3分别低于连接在主位线D1和布线L2之间以及主位线D1和布线L4之间的块选择晶体管BT12和BT13。
-
公开(公告)号：US20050029578A1
公开(公告)日：2005-02-10
申请号：US10931901
申请日：2004-09-01
申请人： Teiichiro Nishizaka
发明人： Teiichiro Nishizaka
IPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/00
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/115 , H01L29/7923 , Y10S257/909
摘要： A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third storage node provided on the substrate and a third gate electrode provided on the third storage node. The first and second gate electrodes are connected common to form word line electrodes. A control gate electrode at right angles to the word line electrodes and a third diffusion region in the substrate surface disposed at a longitudinal end of the control gate electrode are provided. A storage node, Node 1, of interest, with the control gate channel as a drain, is read without the intermediary of the second node, which is not of interest, such that reading of Node 1 unaffected by the second node.
-
9.发明授权Semiconductor memory device having bit lines widely spaced without sacrifice of narrow pitch of source/drain lines of memory cells 失效半导体存储器件具有广泛间隔的位线，而不牺牲存储器单元的源极/漏极线的窄间距
公开(公告)号：US5790450A
公开(公告)日：1998-08-04
申请号：US730677
申请日：1996-10-11
CPC分类号： G11C7/12 , G11C17/126
摘要： When a data bit is read out from a semiconductor read only memory device, a current-mirror type sense amplifier is electrically connected through a bit line, a first selector, a selected memory cell and a second selector to a discharging line so as to check a potential drop on the bit line, and each of the first and second selectors selectively connects the bit line or the discharging line to eight columns of memory cells by increasing the component switching transistors thereof so as to space the bit line from the discharging line, thereby increasing a margin for a bit line contact.
摘要翻译： 当从半导体只读存储器件读出数据位时，电流镜型读出放大器通过位线，第一选择器，选择的存储单元和第二选择器电连接到放电线，以便检查 位线上的电位降，并且第一和第二选择器中的每一个选择性地通过增加其组件切换晶体管将位线或放电线连接到八列存储器单元，以便将位线从放电线放置， 从而增加了位线接触的余量。
-
公开(公告)号：US4981812A
公开(公告)日：1991-01-01
申请号：US451211
申请日：1989-12-15
申请人： Teiichiro Nishizaka
发明人： Teiichiro Nishizaka
IPC分类号： H01L21/76 , H01L21/763 , H01L21/8246 , H01L27/112
CPC分类号： H01L27/1122 , H01L21/763
摘要： In a process for fabricating a semiconductor read only memory, a gate oxidation film is grown on a semiconductor substrate, and a first polycrystalline silicon layer is then grown on the gate oxidation film. The semicondctor substrate is provided with element separating trenches each passing through the gate oxidation film. Then, the element separating trenches are buried with a seccond polycrystalline silicon layer which provides no contamination for a channel portion and the gate oxidation film.
摘要翻译： 在制造半导体只读存储器的工艺中，在半导体衬底上生长栅极氧化膜，然后在栅极氧化膜上生长第一多晶硅层。 所述半浸渍基板具有各自通过所述栅极氧化膜的元件分离沟槽。 然后，分离沟槽的元件被埋入具有不会污染通道部分和栅极氧化膜的多晶硅层。
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.018 秒)
