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    Method for manufacturing semiconductor device and plasma oxidation treatment method
    3.
    发明授权
    Method for manufacturing semiconductor device and plasma oxidation treatment method 有权
    半导体器件制造方法及等离子体氧化处理方法

    公开(公告)号：US09401396B2

    公开(公告)日：2016-07-26

    申请号：US13433563

    申请日：2012-03-29

    申请人： Kanta Abe ,  Hidekazu Miyairi ,  Tetsuhiro Tanaka ,  Takashi Ienaga ,  Yoshitaka Yamamoto

    发明人： Kanta Abe ,  Hidekazu Miyairi ,  Tetsuhiro Tanaka ,  Takashi Ienaga ,  Yoshitaka Yamamoto

    IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L29/04 ,  H01L29/66 ,  H01L21/28 ,  H01L29/786

    CPC分类号： H01L29/04 ,  H01L21/28008 ,  H01L29/66765 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/78678 ,  H01L29/78696

    摘要： Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b≧2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively.

    摘要翻译： 提供一种半导体器件的制造方法，其中通过对含有氮的栅极绝缘膜进行等离子体氧化处理可以抑制薄膜晶体管的特性的劣化。 本发明的一个实施例是一种半导体器件的制造方法，该半导体器件包括薄膜晶体管，该薄膜晶体管包括栅电极，含氮的栅绝缘膜和微晶半导体膜中的沟道区。 该方法包括以下步骤：在包含氢的氧化气体气氛和含有氧原子的氧化气体的栅极绝缘膜上进行等离子体处理，并在栅极绝缘膜上形成微晶半导体膜。 满足式（1），a /b≥2和式（2），b> 0，其中，氢和氧化气体气氛中的氧化气体量分别为a和b。

    Manufacturing method of microcrystalline silicon film and manufacturing method of thin film transistor
    5.
    发明授权
    Manufacturing method of microcrystalline silicon film and manufacturing method of thin film transistor 有权
    微晶硅薄膜的制造方法和薄膜晶体管的制造方法

    公开(公告)号：US08440548B2

    公开(公告)日：2013-05-14

    申请号：US13185742

    申请日：2011-07-19

    申请人： Hidekazu Miyairi ,  Takashi Ienaga ,  Masao Moriguchi ,  Yosuke Kanzaki

    发明人： Hidekazu Miyairi ,  Takashi Ienaga ,  Masao Moriguchi ,  Yosuke Kanzaki

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/32105 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78678 ,  H01L29/78696

    摘要： An object is to provide a manufacturing method of a microcrystalline silicon film with improved adhesion between an insulating film and the microcrystalline silicon film. The microcrystalline silicon film is formed in the following manner. Over an insulating film, a microcrystalline silicon grain having a height that allows the microcrystalline silicon grain to be completely oxidized by later plasma oxidation (e.g., a height greater than 0 nm and less than or equal to 5 nm), or a microcrystalline silicon film or an amorphous silicon film having a thickness that allows the microcrystalline silicon film or the amorphous silicon film to be completely oxidized by later plasma oxidation (e.g., a thickness greater than 0 nm and less than or equal to 5 nm) is formed. Plasma treatment in an atmosphere including oxygen or plasma oxidation is performed on the microcrystalline silicon grain, the microcrystalline silicon film, or the amorphous silicon film, so that a silicon oxide grain or a silicon oxide film is formed over the insulating film. A microcrystalline silicon film is formed over the silicon oxide grain or the silicon oxide film.

    摘要翻译： 本发明的目的是提供一种具有改善的绝缘膜和微晶硅膜之间的粘附性的微晶硅膜的制造方法。 以下述方式形成微晶硅膜。 在绝缘膜上，具有通过稍后的等离子体氧化（例如，高于0nm且小于或等于5nm的高度）使微晶硅晶粒完全氧化的高度的微晶硅晶粒或微晶硅膜 或具有通过稍后的等离子体氧化（例如，厚度大于0nm且小于或等于5nm）使微晶硅膜或非晶硅膜完全氧化的厚度的非晶硅膜。 在微晶硅晶粒，微晶硅膜或非晶硅膜上进行包括氧或等离子体氧化的气氛中的等离子体处理，使得在绝缘膜上形成氧化硅晶粒或氧化硅膜。 在氧化硅晶粒或氧化硅膜上形成微晶硅膜。

    Data processing method and apparatus
    6.
    发明授权
    Data processing method and apparatus 失效
    数据处理方法和装置

    公开(公告)号：US06275923B1

    公开(公告)日：2001-08-14

    申请号：US08883228

    申请日：1997-06-26

    申请人： Takashi Ienaga

    发明人： Takashi Ienaga

    IPC分类号： G06F1500

    CPC分类号： G06F9/30043 ,  G06F12/0638

    摘要： A data processing apparatus and a data processing method for implementing data-tuning rapidly, in which when CPU is operating based on PROM data, it permits operation to implement while referring to data which is rewritten to RAM without stop of the operation. There is provided a CPU core for performing program operation for the purpose of implementing of data processing, a PROM for storing data which is referred at the time of data processing, a register for memorizing a data-stored-address, and a comparator for comparing an address. The comparator is brought into effective when the data-stored-address is outputted while rewriting the RAM during executing the CPU core, comparing the data-stored-address memorized within the register with an address outputted from the CPU core, bringing the RAM selection signal into active when both correspond with each other, while bringing the PROM selection signal into inactive, after receiving thereof the CPU core refers to the data stored within the RAM instead of the data stored within the non-volatile memory, thereby a data-tuning is capable of being realized without stop of operation.

    摘要翻译： 一种用于快速实现数据调谐的数据处理装置和数据处理方法，其中当CPU基于PROM数据进行操作时，允许在参考在RAM中重写的数据而实现操作而不停止该操作。 提供了用于执行数据处理的程序操作的CPU内核，用于存储在数据处理时参考的数据的PROM，用于存储数据存储地址的寄存器和用于比较的比较器 一个地址 当在执行CPU核心期间重写RAM时输出数据存储地址，比较寄存器中存储的数据存储地址与从CPU核心输出的地址，使RAM选择信号 当两者都相互对应时，在使PROM选择信号变为非活动状态的同时，在其接收到CPU核心之后，存储在RAM内的数据代替存储在非易失性存储器内的数据，从而进行数据调整 能够实现而不停止操作。

    Semiconductor memory circuit with bit lines discharging means
    7.
    发明授权
    Semiconductor memory circuit with bit lines discharging means 失效
    具有位线放电装置的半导体存储电路

    公开(公告)号：US6118714A

    公开(公告)日：2000-09-12

    申请号：US314080

    申请日：1999-05-19

    申请人： Takashi Ienaga

    发明人： Takashi Ienaga

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/06

    摘要： A semiconductor memory circuit reduces a current consumed by sense amplifiers, prevents erroneous operation, and can operate at high speed. The semiconductor memory circuit has a plurality of memory blocks each comprising a decoder, a plurality of memory cells, a plurality of sense amplifiers for amplifying potential changes in bit lines, a data latch for latching outputs from the sense amplifiers, a plurality of nMOS transistors for discharging the bit lines, an NAND gate for generating a sense amplifier de-energizing signal RD, and a reference voltage generator. In response to a memory block selecting signal CS, the NAND gate generates the sense amplifier de-energizing signal RD, which is applied to energize the nMOS transistors to discharge the bit lines of a memory block which is not selected.

    摘要翻译： 半导体存储器电路减少由读出放大器消耗的电流，防止错误操作，并且可以高速运行。 半导体存储器电路具有多个存储块，每个存储块包括解码器，多个存储单元，用于放大位线中的电位变化的多个读出放大器，用于锁存来自读出放大器的输出的数据锁存器，多个nMOS晶体管 用于放电位线，用于产生读出放大器去激励信号RD的NAND门和参考电压发生器。 响应于存储块选择信号CS，NAND门产生读出放大器去激励信号RD，其被施加以激励nMOS晶体管以对未被选择的存储器块的位线进行放电。

    Cache memory device of DRAM configuration without refresh function
    8.
    发明授权
    Cache memory device of DRAM configuration without refresh function 失效
    高速缓存存储器件DRAM配置无刷新功能

    公开(公告)号：US5802002A

    公开(公告)日：1998-09-01

    申请号：US784374

    申请日：1997-01-17

    申请人： Takashi Ienaga

    发明人： Takashi Ienaga

    IPC分类号： G11C11/401 ,  G06F12/08 ,  G11C11/406 ,  G11C7/02 ,  G11C7/00

    CPC分类号： G11C11/406

    摘要： In a cache memory device including a DRAM cell array, a DRAM cell circuit is connected to word lines. A sense amplifier and a write amplifier are provided to the DRAM cell circuit for writing a certain data signal into one of memory cells connected to a selected word line. A read amplifier as well as the sense amplifier is provided to read data from one of the memory cells to generate a validity signal for showing whether data of the DRAM cell array is valid or invalid.

    摘要翻译： 在包括DRAM单元阵列的高速缓冲存储器件中，DRAM单元电路连接到字线。 向DRAM单元电路提供读出放大器和写入放大器，用于将特定数据信号写入连接到选定字线的存储单元之一。 提供读取放大器以及读出放大器以从存储器单元之一读取数据，以产生用于显示DRAM单元阵列的数据是有效还是无效的有效信号。

    Lay-out structure of power source potential lines and grand potential lines for semiconductor integrated circuit
    9.
    发明授权
    Lay-out structure of power source potential lines and grand potential lines for semiconductor integrated circuit 失效
    电源电位线的布局结构和半导体集成电路的大电位线

    公开(公告)号：US5442206A

    公开(公告)日：1995-08-15

    申请号：US240549

    申请日：1994-05-11

    申请人： Takashi Ienaga ,  Tomoko Kai

    发明人： Takashi Ienaga ,  Tomoko Kai

    IPC分类号： H01L21/82 ,  H01L27/02 ,  H01L23/48 ,  H01L27/10

    CPC分类号： H01L27/0218 ,  H01L27/0207

    摘要： Among power supply lines for the standard cells provided nearby the corner part of an outer peripheral power supply line (the grand potential, for example) of a macro cell, the power supply line of the power source potential, for example, is connected to an inner peripheral power supply line (the power source potential) through an auxiliary power supply line provided on said corner part. The auxiliary power supply line is formed in L-shape with the first metal layer line and the perpendicular extending second metal layer line connected each other through a contact. Further, the first metal layer line of the auxiliary power supply line is provided so as to cross over the second metal layer line of the outer peripheral power supply line with an insulating layer therebetween. Therefore, the auxiliary power supply line can connect the inner peripheral power supply line and the power source potential line for the standard cell without electrical contact with the outer peripheral power supply line. Therefore, according to the present invention, all of the power supply lines can be connected each other by the automated lay-out technique without occurrence of short and manual modification, therefore the time course required for semiconductor integrated circuit development can be shortened.

    摘要翻译： 在靠近宏小区的外围电源线（例如宏电位）的角部附近提供的标准电池的电源线中，电源电位的电源线例如连接到 内部电源线（电源电位）通过设置在所述角部上的辅助电源线。 辅助电源线形成为L形，第一金属层线和垂直延伸的第二金属层线通过接触彼此连接。 此外，辅助电源线的第一金属层线被设置成跨越外周电源线的第二金属层线，其间具有绝缘层。 因此，辅助电源线可以连接内部电源线和标准电池的电源电位线，而不与外部电源线电接触。 因此，根据本发明，可以通过自动铺设技术将所有的电源线彼此连接，而不会发生短暂的和手动的修改，因此可以缩短半导体集成电路开发所需的时间。