公开(公告)号：US07145818B2

公开(公告)日：2006-12-05

申请号：US10806417

申请日：2004-03-23

申请人： Tetsuya Fukuoka ,  Mikio Yamagishi

发明人： Tetsuya Fukuoka ,  Mikio Yamagishi

IPC分类号： G11C29/30

CPC分类号： G11C29/1201 ,  G01R31/318536 ,  G11C29/46 ,  G11C2029/3202

摘要： A semiconductor integrated circuit device is provided with a diagnosis circuit, which does not increase the delay of a logic element in normal operation. In a latch provided at the output of a memory or at the input of a logic stage, a signal selector is provided in the feedback loop of the latch. The selector is switched in correspondence with the operation mode, such that it transfers the feedback signal in normal operation, while it transfers the test signal in a test mode, in order to prevent the delay from increasing in the signal selector on the main path in normal operation.

摘要翻译： 半导体集成电路器件设置有诊断电路，其不会在正常操作中增加逻辑元件的延迟。 在设置在存储器的输出处或在逻辑级的输入处的锁存器中，在锁存器的反馈回路中提供信号选择器。 选择器与操作模式相对应地切换，使得它在正常操作中传送反馈信号，同时在测试模式下传送测试信号，以防止在主路径上的信号选择器中的延迟增加 普通手术。

公开(公告)号：US06287124B1

公开(公告)日：2001-09-11

申请号：US09204375

申请日：1998-12-02

申请人： Atsushi Yamaura ,  Mikio Yamagishi

发明人： Atsushi Yamaura ,  Mikio Yamagishi

IPC分类号： G09B1900

CPC分类号： G09B19/00 ,  G09B15/00

摘要： Target music piece, which a trainee player aims to perform well through practice, is designated by a user or player from among various music genres such as classical music, popular music and enka (Japanese popular ballads). Lesson information supplying section supplies lesson information prepared by combining information descriptive of a plurality of training music pieces bearing particular relations to the target music piece, to allow the player to become skillful enough for performing the designated target music piece. The lesson information comprises a combination of information descriptive of a plurality of optimum training music pieces selected on the basis of all kinds of musical information, such as a music genre, key, rhythm and beat, of the target music piece. Control section controls player's performance practice on the basis of the lesson information supplied by the lesson information supplying section. This arrangement enables the player to acquire a skill necessary for performing the target music piece in a short time and with a small amount of training.

摘要翻译： 受训玩家旨在通过实践表现良好的目标音乐作品由用户或玩家从诸如古典音乐，流行音乐和enka（日本流行民谣）的各种音乐流派中指定。 课程信息提供部分通过将描述具有特定关系的多个训练音乐片段的信息组合到目标音乐片段来提供准备的课程信息，以允许玩家熟练地执行指定的目标音乐片段。 课程信息包括描述基于目标乐曲的各种音乐信息（诸如音乐类型，键，节奏和节拍）所选择的多个最佳训练乐曲的信息的组合。 控制部分根据课程信息提供部分提供的课程信息来控制玩家的表演练习。 这种安排使得玩家能够在短时间内以少量的训练获得执行目标乐曲所需的技能。

公开(公告)号：US5479745A

公开(公告)日：1996-01-02

申请号：US229795

申请日：1994-04-19

申请人： Yoshinari Kawai ,  Fumihiro Oyama ,  Mikio Yamagishi

发明人： Yoshinari Kawai ,  Fumihiro Oyama ,  Mikio Yamagishi

IPC分类号： E04F15/00 ,  E04F15/024 ,  E04B9/00

CPC分类号： E04F15/02464

摘要： Floor panel support legs support floor panels atop a floor slab and a double floor device uses such floor panel support legs. Each floor support leg is constituted by a pair of cylindrical first and second pedestal members and a fixing member for fixing the relative position between the first and second pedestal members, the first and second pedestal members having bottoms at their axial one end portions and thread portions at their inner and outer circumferential surfaces respectively so that they are thread-engaged with each other through their thread portions. The axial height of the support leg is set by the degree of thread engagement between the first and second pedestal members and the thus set height is fixed by the fixing member. Such support legs are arranged between a floor slab and floor panels at butted portions of the floor panels to support the floor panels to thereby constitute a double floor device. Thus, the support legs are capable of strongly supporting floor panels at a low position from a floor slab to thereby provide a low double floor device.

摘要翻译： 地板支撑腿支撑地板上的地板，双层地板装置使用这种地板支撑腿。 每个地板支撑腿由一对圆柱形的第一和第二基座构件和用于固定第一和第二基座构件之间的相对位置的固定构件构成，第一和第二基座构件在其轴向一个端部具有底部和螺纹部分 在它们的内周面和外圆周表面上，使得它们通过它们的螺纹部分彼此螺纹接合。 支撑腿的轴向高度由第一和第二基座构件之间的螺纹接合程度设定，并且由此固定的高度由固定构件固定。 这种支撑腿布置在地板和地板之间的地板和地板镶板的对接部分之间，以支撑地板镶板，从而构成双层地板装置。 因此，支撑腿能够在从地板的低位置强烈地支撑地板镶板，从而提供低的双层地板装置。

公开(公告)号：US5387809A

公开(公告)日：1995-02-07

申请号：US820005

申请日：1992-01-13

申请人： Mikio Yamagishi ,  Kazuo Koide ,  Tetsuo Nakano

发明人： Mikio Yamagishi ,  Kazuo Koide ,  Tetsuo Nakano

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H01L27/02

CPC分类号： H01L27/11898

摘要： A semiconductor integrated circuit device includes an interface corresponding to a relatively high signal level; an interface corresponding to a relatively low signal level; and an internal circuit made responsive to a signal through either interface for generating a signal to be transmitted to the other interface. The interface corresponding to a relatively high level, the internal circuit, and a drive control circuit constituting the input circuit and output circuit of the interface corresponding to a relatively low level are operated by an operating voltage corresponding to the relatively high level. An output element of the output circuit in the interface corresponding to a relatively low level, which is to be driven by the drive control circuit, is operated by an operating voltage corresponding to the relatively low level.

摘要翻译： 半导体集成电路器件包括对应于较高信号电平的接口; 对应于相对低的信号电平的接口; 以及通过任一接口响应于信号产生要传输到另一接口的信号的内部电路。 对应于相对较高电平的接口，内部电路和构成对应于相对低电平的接口的输入电路和输出电路的驱动控制电路由对应于较高电平的工作电压来操作。 在由与驱动控制电路驱动的较低电平对应的接口中的输出电路的输出元件由对应于较低电平的工作电压进行操作。

公开(公告)号：US5365091A

公开(公告)日：1994-11-15

申请号：US65053

申请日：1993-05-24

申请人： Mikio Yamagishi

发明人： Mikio Yamagishi

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H01L27/02 ,  H01L27/10

CPC分类号： H01L27/11898 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14

摘要： A semiconductor integrated circuit device comprises a plurality of peripheral power supply lines extending along the periphery of an internal circuit region formed in a semiconductor chip. Bonding pads are arranged outside of the peripheral power supply lines, wherein the wiring layers used in the peripheral power supply line arranged at the outermost periphery are made less by one than those used in the inner peripheral power supply line adjacent to the outermost peripheral power supply line. Reduced wiring layers are formed with power leading lines for connecting the inner peripheral power supply line and the bonding pads. Moreover, the power leading lines for connecting the outermost peripheral power supply lines and the bonding pads are formed of the same wiring layer as that of the outermost peripheral power supply line. The semiconductor integrated circuit device is further constructed such that there are arranged along the peripheral of the internal circuit region a plurality of I/O cells and high drive power output buffer circuits which include two or more adjacent ones of the plurality of I/O cells and which are adapted to be fed with the supply voltages from the peripheral power supply lines. Moreover, predetermined ones of external terminals assigned to the plurality of I/O cells constituting the high drive power output buffer circuits are used as terminals for feeding the supply voltages to the plurality of peripheral power supply lines.

摘要翻译： 半导体集成电路器件包括沿形成在半导体芯片中的内部电路区域的周边延伸的多个外围电源线。 接合焊盘布置在外围电源线的外部，其中在最外周配置的周边电源线中使用的布线层比在与最外周电源相邻的内周电源线中使用的布线层少一个 线。 形成有用于连接内周电源线和接合焊盘的电力引线的减少的布线层。 此外，用于连接最外周电源线和接合焊盘的电源引出线由与最外周电源线相同的布线层形成。 半导体集成电路器件进一步被构造成使得沿着内部电路区域的外围布置多个I / O单元和包括多个I / O单元中的两个或更多个相邻I / O单元的高驱动功率输出缓冲电路 并且适于从外围电源线馈送电源电压。 此外，分配给构成高驱动功率输出缓冲电路的多个I / O单元的外部终端的预定的一部分被用作将电源电压馈送到多个外围电源线的端子。

公开(公告)号：US4977615A

公开(公告)日：1990-12-11

申请号：US352775

申请日：1989-05-16

申请人： Hirohisa Suzuki ,  Akira Kabashima ,  Mikio Yamagishi ,  Ryuichi Ogawa

发明人： Hirohisa Suzuki ,  Akira Kabashima ,  Mikio Yamagishi ,  Ryuichi Ogawa

IPC分类号： H04B7/08

CPC分类号： H04B7/0805

摘要： A diversity receiver includes first and second antennae for receiving an RF signal, and an antenna switching circuit for selecting one of the first and second antennae. A first detection circuit having a high sensitivity, and a second detection circuit having a low sensitivity are provided, each detecting a noise signal contained within the received RF signal in different sensitivity. A field strength detection circuit is provided for detecting a field strength of the received RF signal, and a selection circuit is provided for selecting either one of the first and second detection circuits according to the output signal of the field strength detection circuit, and for providing a switching signal to the antenna switching circuit. Thus, when the field strength is relatively strong, the first detection circuit with high sensitivity is used for the noise detection, and when the field strength is relatively weak, the second detection circuit with low sensitivity is used for the noise detection.

公开(公告)号：US4972482A

公开(公告)日：1990-11-20

申请号：US244074

申请日：1988-09-13

申请人： Kazuhisa Ishiguro ,  Mikio Yamagishi

发明人： Kazuhisa Ishiguro ,  Mikio Yamagishi

IPC分类号： H04B1/16

CPC分类号： H04B1/1692

摘要： Levels of a stereo sum signal and a stereo difference signal are detected by first and second level detectors (7, 9), respectively. Outputs of the first and second level detectors (7, 9) are compared with each other by a comparator (10). A voltage controlled amplifier (4) is responsive to an output of the comparator (10) for changing a level of the stereo difference signal, when a broadcasting signal including only either one of a left stereo signal and a right stereo signal is received, such that the levels of the stereo sums signal and the stereo difference signal are equal to each other.

公开(公告)号：US4944010A

公开(公告)日：1990-07-24

申请号：US269903

申请日：1988-11-10

申请人： Kazuhisa Ishiguro ,  Mikio Yamagishi

发明人： Kazuhisa Ishiguro ,  Mikio Yamagishi

IPC分类号： H03D1/22 ,  H04H1/00 ,  H04H40/45

CPC分类号： H03D1/2236 ,  H03D1/2209

摘要： A stereo demodulator of a matrix system comprises: a first amplifier (23, 24, 25) for negative feedback amplification of a stereophonic composite signal, a first voltage-current converter (26) for detecting a current-form stereophonic sum signal responsive to a voltage output of the first amplifier, a non-inversion amplifier (27) for negative feedback non-inversion amplification of the stereophonic composite signal, an inversion amplifier (28) for negative feedback inversion amplification of the stereophonic composite signal, a second voltage-current converter (29, 38) for outputting a first current-form stereophonic subchannel signal responsive to a voltage output of the non-inversion amplifier (27), a third voltage-current converter (30, 39) for supplying a current-form signal stereophonic subchannel signal responsive to a voltage output from the inversion amplifier (28), a difference signal demodulator (31) for providing stereophonic difference signals of opposite phases in the form of current signals from the outputs of the second and third voltage-current converters, and an matrix circuit (41) for performing matrix processing on the received stereophonic sum signal from the first voltage-current converter and the stereophonic difference signals from the difference signal demodulator (31) and outputting right and left stereophonic signals in a voltage signal form.

公开(公告)号：US5038056A

公开(公告)日：1991-08-06

申请号：US515683

申请日：1990-04-26

申请人： Kazuo Koide ,  Mikio Yamagishi ,  Kazutaka Mori

发明人： Kazuo Koide ,  Mikio Yamagishi ,  Kazutaka Mori

IPC分类号： H03K19/003

CPC分类号： H03K19/00361

摘要： In order to reduce undesirable output noise, an output circuit is provided which includes a first output MOSFET which is interposed between an output terminal and a first power source voltage, and a second output MOSFET which is interposed between the output terminal and a second power source voltage. In particular, in accordance with one aspect of the invention, a feedback circuit is interposed between the output terminal and the gate of the first output MOSFET or/and between the output terminal and the gate of the second output MOSFET to negatively feedback voltage to provide a gentle level change for the output voltage. In other embodiments, a short-circuit arrangement is provided which is interposed between the gate and source of the first output MOSFET or/and between the gate and source of the second output MOSFET. The short-circuit arrangement is temporarily held in a transferring state at the initial stage of a process in which the corresponding first or second output MOSFET is turned on to provide the desired gentle level change.

摘要翻译： 为了减少不期望的输出噪声，提供了一种输出电路，其包括介于输出端和第一电源电压之间的第一输出MOSFET，以及插在输出端和第二电源之间的第二输出MOSFET 电压。 特别地，根据本发明的一个方面，反馈电路被插入在第一输出MOSFET的输出端和栅极之间或/和第二输出MOSFET的输出端和栅极之间，以反馈电压以提供 输出电压的电平变化较小。 在其他实施例中，提供了一种短路布置，其插入在第一输出MOSFET的栅极和源极之间或/以及第二输出MOSFET的栅极和源极之间。 在相应的第一或第二输出MOSFET导通的过程的初始阶段，短路装置暂时保持在转移状态，以提供期望的缓和电平变化。

公开(公告)号：US5497263A

公开(公告)日：1996-03-05

申请号：US117525

申请日：1993-09-07

申请人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

发明人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

IPC分类号： G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03H11/26 ,  H03K17/296

CPC分类号： H03K5/133 ,  G06F1/10 ,  H03K2005/00071 ,  H03K2005/00097 ,  H03K2005/00195

摘要： A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

摘要翻译： 一种可变延迟电路，包括延迟装置，每个延迟装置具有连续连接的多个延迟单元，延迟装置的一些延迟单元连接到信号传输线，其中通过激活或者使多个延迟单元激活来控制延迟时间 根据施加到分别为所述多个延迟单元提供的控制输入端子的控制信号。 一种用于向逻辑电路块提供第二时钟信号的时钟信号提供装置，所述时钟信号提供装置具有用于产生第一时钟信号和参考信号的时钟信号发生器和用于调整第一时钟的相位的相位调整装置 信号相位于第一时钟信号和参考信号之间的相位差，并输出相位调整信号作为第二时钟信号，其中相位调整单元包括能够在第一时钟的初始调整中延迟操作的第一可变延迟电路 信号，与第一可变延迟电路串联布置的第二可变延迟电路，用于在初始调整之后执行延迟操作;以及控制电路，用于控制第一和第二可变延迟电路的延迟时间。