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    Field effect transistor and method for fabricating the same
    4.
    发明申请
    Field effect transistor and method for fabricating the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US20060124962A1

    公开(公告)日：2006-06-15

    申请号：US11297386

    申请日：2005-12-09

    申请人： Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

    发明人： Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

    IPC分类号： H01L31/0328

    CPC分类号： H01L21/28581 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

    摘要： A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other. An opening having an insulating film on its inner wall is formed in a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode so as to expose the first semiconductor layer therein. A gate electrode is formed in the opening to be in contact with the insulating film and the first semiconductor layer on the bottom of the opening.

    摘要翻译： 场效应晶体管包括由多个半导体膜的多层构成的第一半导体层和形成在第一半导体层上的第二半导体层。 源电极和漏电极形成在第二半导体层上以彼此间隔开。 在夹在源电极和漏极之间的第二半导体层的一部分中形成有在其内壁上具有绝缘膜的开口，以便在其中露出第一半导体层。 在开口部形成有与绝缘膜和开口底部的第一半导体层接触的栅电极。

    Field effect transistor and method for fabricating the same
    5.
    发明授权
    Field effect transistor and method for fabricating the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US07834380B2

    公开(公告)日：2010-11-16

    申请号：US11297386

    申请日：2005-12-09

    申请人： Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

    发明人： Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

    IPC分类号： H01L29/66

    CPC分类号： H01L21/28581 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

    摘要： A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other. An opening having an insulating film on its inner wall is formed in a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode so as to expose the first semiconductor layer therein. A gate electrode is formed in the opening to be in contact with the insulating film and the first semiconductor layer on the bottom of the opening.

    摘要翻译： 场效应晶体管包括由多个半导体膜的多层构成的第一半导体层和形成在第一半导体层上的第二半导体层。 源电极和漏电极形成在第二半导体层上以彼此间隔开。 在夹在源电极和漏极之间的第二半导体层的一部分中形成有在其内壁上具有绝缘膜的开口，以便在其中露出第一半导体层。 在开口部形成有与绝缘膜和开口底部的第一半导体层接触的栅电极。

    NITRIDE SEMICONDUCTOR DEVICE
    7.
    发明申请
    NITRIDE SEMICONDUCTOR DEVICE 有权
    氮化物半导体器件

    公开(公告)号：US20120146093A1

    公开(公告)日：2012-06-14

    申请号：US13372065

    申请日：2012-02-13

    申请人： Daisuke SHIBATA ,  Masahiro Hikita ,  Hidetoshi Ishida ,  Tetsuzo Ueda

    发明人： Daisuke SHIBATA ,  Masahiro Hikita ,  Hidetoshi Ishida ,  Tetsuzo Ueda

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7786 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/7787 ,  H01L29/872

    摘要： A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semiconductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 102 includes a first nitride semiconductor layer, a second nitride semiconductor layer, and a p-type third nitride semiconductor layer 124 sequentially formed on the substrate. The third nitride semiconductor layer contains p-type impurities, and is selectively formed between the first ohmic electrode and the Schottky electrode in contact with the Schottky electrode.

    摘要翻译： 氮化物半导体器件包括形成在衬底上的半导体层，在半导体多层上彼此间隔开的第一欧姆电极和肖特基电极; 以及覆盖半导体多层的顶部的钝化膜。 半导体层叠体102包括顺序形成在基板上的第一氮化物半导体层，第二氮化物半导体层和p型第三氮化物半导体层124。 第三氮化物半导体层含有p型杂质，并且选择性地形成在与肖特基电极接触的第一欧姆电极和肖特基电极之间。

    Field effect transistor with main surface including C-axis
    8.
    发明授权
    Field effect transistor with main surface including C-axis 有权
    场效应晶体管主表面包括C轴

    公开(公告)号：US08089096B2

    公开(公告)日：2012-01-03

    申请号：US11470316

    申请日：2006-09-06

    申请人： Hidetoshi Ishida ,  Masayuki Kuroda ,  Tetsuzo Ueda

    发明人： Hidetoshi Ishida ,  Masayuki Kuroda ,  Tetsuzo Ueda

    IPC分类号： H01L29/778 ,  H01L29/04

    CPC分类号： H01L29/7787 ,  H01L29/2003

    摘要： A normally-off type field effect transistor includes: a first semiconductor layer which is made of a first hexagonal crystal with 6 mm symmetry and has a main surface including a C-axis of the first hexagonal crystal; a second semiconductor layer which is formed on the main surface of the first semiconductor layer and is made of a second hexagonal crystal with 6 mm symmetry having a band gap different from a band gap of the first hexagonal crystal; and a gate electrode, a source electrode and a drain electrode that are formed on the second semiconductor layer. Here, the film thickness of the first nitride semiconductor layer is 1.5 μm or less and the second semiconductor layer is doped with impurities at a dose of 1×1013 cm−2 or more.

    摘要翻译： 常关型场效应晶体管包括：第一半导体层，其由具有6mm对称性的第一六边形晶体制成并且具有包括第一六边形晶体的C轴的主表面; 第二半导体层，其形成在所述第一半导体层的主表面上，并且由具有与所述第一六边形晶体的带隙不同的带隙的6mm对称的第二六边形晶体制成; 以及形成在第二半导体层上的栅电极，源电极和漏电极。 这里，第一氮化物半导体层的膜厚为1.5μm以下，第二半导体层以1×1013cm-2以上的剂量掺杂杂质。

    Semiconductor device and manufacturing method thereof
    9.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07595544B2

    公开(公告)日：2009-09-29

    申请号：US11382994

    申请日：2006-05-12

    申请人： Masayuki Kuroda ,  Hidetoshi Ishida ,  Tetsuzo Ueda

    发明人： Masayuki Kuroda ,  Hidetoshi Ishida ,  Tetsuzo Ueda

    IPC分类号： H01L29/04

    CPC分类号： H01L29/7787 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66462

    摘要： An object of the present invention is to provide a semiconductor device and a manufacturing method thereof which can realize a normally-off field-effect transistor made of a III group nitride semiconductor. The present invention includes: placing a sapphire substrate in a crystal growth chamber; forming a low-temperature GaN buffer layer made of GaN as the III group nitride semiconductor, on a main surface of the sapphire substrate by a MOCVD method; and forming a GaN layer on the low-temperature GaN buffer layer by the MOCVD method. Here, a [11-20] axis of the GaN layer is perpendicular to the main surface of the sapphire substrate.

    摘要翻译： 本发明的目的是提供一种能够实现由III族氮化物半导体构成的常关的场效应晶体管的半导体器件及其制造方法。 本发明包括：将蓝宝石衬底放置在晶体生长室中; 通过MOCVD方法在蓝宝石衬底的主表面上形成由GaN构成的III族氮化物半导体的低温GaN缓冲层; 并通过MOCVD法在低温GaN缓冲层上形成GaN层。 这里，GaN层的[11-20]轴垂直于蓝宝石衬底的主表面。

    Field effect transistor and method of manufacturing the same
    10.
    发明授权
    Field effect transistor and method of manufacturing the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US08441035B2

    公开(公告)日：2013-05-14

    申请号：US13150574

    申请日：2011-06-01

    申请人： Masahiro Hikita ,  Hidetoshi Ishida ,  Tetsuzo Ueda

    发明人： Masahiro Hikita ,  Hidetoshi Ishida ,  Tetsuzo Ueda

    IPC分类号： H01L29/778

    CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/808

    摘要： The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.

    摘要翻译： 本发明的目的是提供一种能够增加阈值电压以及降低导通电阻的FET和FET的制造方法。 本发明的FET包括第一未掺杂的GaN层; 形成在第一未掺杂的GaN层上的第一未掺杂的AlGaN层，其带隙能量大于第一未掺杂的GaN层的带隙能量; 形成在第一未掺杂的AlGaN层上的第二未掺杂的GaN层; 形成在所述第二未掺杂GaN层上的第二未掺杂AlGaN层，具有大于所述第二未掺杂GaN层的带隙能量的带隙能量; 形成在第二未掺杂AlGaN层的凹部中的p型GaN层; 形成在p型GaN层上的栅电极; 以及形成在所述栅电极的两个横向区域中的源电极和漏电极，其中在所述第一未掺杂的GaN层和所述第一未掺杂的AlGaN层之间的异质结界面处形成沟道。