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公开(公告)号：US11791170B2
公开(公告)日：2023-10-17
申请号：US17238151
申请日：2021-04-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H01L21/565 , B29C33/0022 , B29C33/44 , B29C45/14467 , H01L21/4821 , H01L21/561 , H01L23/3107 , H01L23/49537 , H01L23/49555 , H01L2924/1815
Abstract: A method of making semiconductor packages includes providing a first lead frame having a first plurality of semiconductor dies arranged along a first longitudinal axis, each of the first plurality of semiconductor dies having a first number of metal contacts; providing a second lead frame having a second plurality of semiconductor dies arranged along a second longitudinal axis, each of the second plurality of semiconductor dies having a second number of metal contacts, the second number of metal contacts different than the first number of metal contacts; and covering the first plurality of semiconductor dies in a first mold using a common semiconductor die cavity; covering the second plurality of semiconductor dies in a second mold using the common semiconductor die cavity.
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Patent Agency Ranking
公开(公告)号：US11626350B2
公开(公告)日：2023-04-11
申请号：US16839216
申请日：2020-04-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Chong Han Lim , Lee Han Meng@Eugene Lee , Anis Fauzi Bin Abdul Aziz , Wei Fen Sueann Lim , Siew Kee Lee
IPC: H01L23/495 , H01L21/56 , H01L21/78 , H01L23/31 , H01L21/00 , H01L25/075 , H01L21/60
Abstract: A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.
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公开(公告)号：US12119289B2
公开(公告)日：2024-10-15
申请号：US18328896
申请日：2023-06-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yee Gin Tea , Chong Han Lim
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49548 , H01L21/4825 , H01L21/4828 , H01L21/565 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/49513 , H01L23/4952 , H01L23/49541 , H01L23/49582 , H01L24/06 , H01L24/29 , H01L24/49 , H01L2924/181
Abstract: In some examples, a semiconductor package comprises a die pad, a semiconductor die on the die pad, and a mold compound covering the die pad and the semiconductor die. The semiconductor package includes a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2. The mold compound is coupled to the roughened surface. The semiconductor package includes a bond wire coupling the semiconductor die to the roughened surface. The bond wire is directly coupled to the roughened surface without a precious metal positioned therebetween.
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公开(公告)号：US20170213781A1
公开(公告)日：2017-07-27
申请号：US15003238
申请日：2016-01-21
Applicant: Texas Instruments Incorporated
Inventor： Lee Han Meng@Eugene Lee , Chong Han Lim , You Chye How
IPC: H01L23/495 , H01L21/48
CPC classification number: H01L23/49537 , H01L21/4825 , H01L21/4828 , H01L21/4839 , H01L23/49541 , H01L23/49568 , H01L23/49575 , H01L23/49582 , H01L23/49589 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/16245 , H01L2224/291 , H01L2224/32245 , H01L2224/73253 , H01L2224/81815 , H01L2224/83192 , H01L2224/92225 , H01L2224/97 , H01L2924/15153 , H01L2224/81 , H01L2924/014 , H01L2924/00014
Abstract: An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.
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公开(公告)号：US11715678B2
公开(公告)日：2023-08-01
申请号：US17157557
申请日：2021-01-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yee Gin Tea , Chong Han Lim
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/00
CPC classification number: H01L23/49548 , H01L21/4825 , H01L21/4828 , H01L21/565 , H01L23/3107 , H01L23/3114 , H01L23/4952 , H01L23/49503 , H01L23/49513 , H01L23/49541 , H01L23/49582 , H01L24/06 , H01L2924/181
Abstract: In some examples, a semiconductor package comprises a die pad, a semiconductor die on the die pad, and a mold compound covering the die pad and the semiconductor die. The semiconductor package includes a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2. The mold compound is coupled to the roughened surface. The semiconductor package includes a bond wire coupling the semiconductor die to the roughened surface. The bond wire is directly coupled to the roughened surface without a precious metal positioned therebetween.
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公开(公告)号：US10381293B2
公开(公告)日：2019-08-13
申请号：US15003238
申请日：2016-01-21
Applicant: Texas Instruments Incorporated
Inventor： Lee Han Meng@Eugene Lee , Chong Han Lim , You Chye How
IPC: H01L21/48 , H01L23/00 , H01L23/495
Abstract: An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.
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