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公开(公告)号:US11626350B2
公开(公告)日:2023-04-11
申请号:US16839216
申请日:2020-04-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Chong Han Lim , Lee Han Meng@Eugene Lee , Anis Fauzi Bin Abdul Aziz , Wei Fen Sueann Lim , Siew Kee Lee
IPC: H01L23/495 , H01L21/56 , H01L21/78 , H01L23/31 , H01L21/00 , H01L25/075 , H01L21/60
Abstract: A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.
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公开(公告)号:US10943856B2
公开(公告)日:2021-03-09
申请号:US16460665
申请日:2019-07-02
Applicant: Texas Instruments Incorporated
Inventor: Yien Sien Khoo , Siew Kee Lee
IPC: H01L23/49 , H01L23/31 , H01F1/14 , H01F1/36 , H01L23/495 , H01F27/02 , H01F27/29 , H01L21/48 , H01L49/02 , H01L21/56 , H01F27/255 , H01F1/147 , H02M3/158 , H01L23/64
Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 μms.
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公开(公告)号:US20180082930A1
公开(公告)日:2018-03-22
申请号:US15693059
申请日:2017-08-31
Applicant: Texas Instruments Incorporated
Inventor: Yien Sien Khoo , Siew Kee Lee
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/31 , H01L49/02 , H01F1/147 , H01F1/36 , H01F27/29 , H01F27/255
CPC classification number: H01L23/49541 , H01F1/14766 , H01F1/36 , H01F27/027 , H01F27/255 , H01F27/29 , H01F27/292 , H01F2027/295 , H01L21/4825 , H01L21/565 , H01L23/3107 , H01L23/3114 , H01L23/495 , H01L23/49513 , H01L23/4952 , H01L23/49537 , H01L23/49575 , H01L23/645 , H01L28/10 , H01L2924/1206 , H01L2924/19042 , H02M3/158
Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 μms.
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公开(公告)号:US10340210B2
公开(公告)日:2019-07-02
申请号:US15693059
申请日:2017-08-31
Applicant: Texas Instruments Incorporated
Inventor: Yien Sien Khoo , Siew Kee Lee
IPC: H01L23/49 , H01L23/31 , H01L23/64 , H01F1/14 , H01F1/36 , H01F27/25 , H01F27/29 , H01L23/495 , H01L21/48 , H01L21/56 , H01L49/02 , H01F1/147 , H01F27/255 , H01F27/02 , H02M3/158
Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 μms.
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公开(公告)号:US09123626B1
公开(公告)日:2015-09-01
申请号:US14192402
申请日:2014-02-27
Applicant: Texas Instruments Incorporated
Inventor: You Chye How , Siew Kee Lee , Huay Yann Tay
IPC: H01L23/48 , H01L29/40 , H01L21/00 , H01L25/16 , H01L23/495 , H01L23/528 , H01L23/00 , H01L23/31 , H01L23/532 , H01L21/768 , H01L21/56 , H01L25/00
CPC classification number: H01L25/165 , H01L21/561 , H01L23/3107 , H01L23/481 , H01L23/49541 , H01L23/53214 , H01L23/53228 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/06102 , H01L2224/06181 , H01L2224/131 , H01L2224/16245 , H01L2224/16265 , H01L2224/1703 , H01L2224/81801 , H01L2224/9212 , H01L2224/9222 , H01L2224/94 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/14 , H01L2924/181 , H01L2924/19104 , H01L2924/19106 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/81 , H01L2924/00014
Abstract: A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die.
Abstract translation: 一种用于封装集成电路管芯的方法,使得每个封装包括具有安装到管芯的背表面,活性表面或后表面和有源表面的集成无源元件的管芯。
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公开(公告)号:US11569152B2
公开(公告)日:2023-01-31
申请号:US16254853
申请日:2019-01-23
Applicant: Texas Instruments Incorporated
IPC: H01L23/495 , H01L21/56 , H01L23/31
Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.
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公开(公告)号:US20150243639A1
公开(公告)日:2015-08-27
申请号:US14192402
申请日:2014-02-27
Applicant: Texas Instruments Incorporated
Inventor: You Chye How , Siew Kee Lee , Huay Yann Tay
IPC: H01L25/16 , H01L23/528 , H01L23/00 , H01L25/00 , H01L23/31 , H01L23/532 , H01L21/768 , H01L21/56 , H01L23/495 , H01L23/48
CPC classification number: H01L25/165 , H01L21/561 , H01L23/3107 , H01L23/481 , H01L23/49541 , H01L23/53214 , H01L23/53228 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/06102 , H01L2224/06181 , H01L2224/131 , H01L2224/16245 , H01L2224/16265 , H01L2224/1703 , H01L2224/81801 , H01L2224/9212 , H01L2224/9222 , H01L2224/94 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/14 , H01L2924/181 , H01L2924/19104 , H01L2924/19106 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/81 , H01L2924/00014
Abstract: A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die.
Abstract translation: 一种用于封装集成电路管芯的方法,使得每个封装包括具有安装到管芯的背表面,活性表面或后表面和有源表面的集成无源元件的管芯。
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公开(公告)号:US20200235042A1
公开(公告)日:2020-07-23
申请号:US16254853
申请日:2019-01-23
Applicant: Texas Instruments Incorporated
IPC: H01L23/495 , H01L23/31 , H01L21/56
Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.
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公开(公告)号:US20190326203A1
公开(公告)日:2019-10-24
申请号:US16460665
申请日:2019-07-02
Applicant: Texas Instruments Incorporated
Inventor: Yien Sien Khoo , Siew Kee Lee
IPC: H01L23/495 , H01F1/36 , H01F27/02 , H01F27/29 , H01L21/48 , H01L49/02 , H01L21/56 , H01F27/255 , H01F1/147 , H01L23/31
Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 μms.
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公开(公告)号:US20150053586A1
公开(公告)日:2015-02-26
申请号:US13973760
申请日:2013-08-22
Applicant: Texas Instruments Incorporated
Inventor: You Chye How , Siew Kee Lee , Huay Yann Tay
IPC: B65D85/62
CPC classification number: H05K13/0084 , Y10T428/13
Abstract: A carrier tape for transporting electronic components having a linearly displaceable continuous web and a plurality of pocket structures connected to the continuous web. The pocket structures are adapted to receive the electronic components. Each of the plurality of pocket structures defines an opening to enable passage of the electronic component into the pocket structure. Each of the pocket structures define at least one tab that is adapted to retain an electronic component in the pocket structure without a closure member.
Abstract translation: 一种用于运送具有线性可移动的连续卷材的电子部件的载带和连接到连续卷材的多个袋结构。 口袋结构适于接收电子部件。 多个凹穴结构中的每一个限定了一个开口,以使得电子部件能够通过到口袋结构中。 每个凹穴结构限定至少一个凸片,其适于将电子部件保持在口袋结构中而没有闭合部件。
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