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公开(公告)号：US20240153903A1
公开(公告)日：2024-05-09
申请号：US18414125
申请日：2024-01-16
IPC分类号： H01L23/00 , H01L21/027
CPC分类号： H01L24/13 , H01L21/027 , H01L24/04 , H01L24/11 , H01L2221/1068 , H01L2224/022 , H01L2224/0401 , H01L2224/1146 , H01L2224/1147 , H01L2224/13144 , H01L2224/13147 , H01L2924/014 , H01L2924/177
摘要： In a described example, an apparatus includes: a semiconductor die having a device side surface; bond pads on the semiconductor die on the device side surface; post connects having a proximate end on the bond pads and extending from the bond pads to a distal end, the diameter of the post connects at the proximate end being the same as the diameter of the post connects at the distal end; polyimide material covering sides of the post connects and covering at least a portion of the bond pads; and solder bumps on the distal end of the post connects.
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公开(公告)号：US20230317658A1
公开(公告)日：2023-10-05
申请号：US17710201
申请日：2022-03-31
IPC分类号： H01L23/00 , H01L23/495
CPC分类号： H01L24/11 , H01L24/03 , H01L23/495 , H01L24/06 , H01L24/13 , H01L24/81 , H01L2224/0312 , H01L2224/1146 , H01L2224/13147 , H01L2224/81815 , H01L2224/10126 , H01L2224/1301 , H01L2224/13144 , H01L2224/13116 , H01L2224/13111 , H01L2224/13139 , H01L2924/014
摘要： A described example includes: a semiconductor die having bond pads on a device side surface; a passivation layer overlying the device side surface of the semiconductor die with openings in the passivation layer, the passivation layer having a planar surface facing away from the device side surface of the semiconductor die; post connects formed on the bond pads and in the openings in the passivation layer, the post connects having a proximate end on the bond pads and extending from the bond pads to a distal end that lies beneath the planar surface of the passivation layer; solder at the distal ends of the post connects and contacting sidewalls of the openings in the passivation layer; and solder joints formed between the solder at the distal ends of the post connects and a package substrate, the device side surface of the semiconductor die facing the package substrate.
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公开(公告)号：US20210320074A1
公开(公告)日：2021-10-14
申请号：US17356302
申请日：2021-06-23
发明人： Rafael Jose Lizares Guevara , Aniceto Tabangcura Rabilas, JR. , Ray Fredric Solis de Asis , Sylvester Tigno Sanchez , Alvin Lopez Andaya
IPC分类号： H01L23/00 , H01L21/56 , H01L23/495
摘要： In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.
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公开(公告)号：US20240128204A1
公开(公告)日：2024-04-18
申请号：US18391463
申请日：2023-12-20
CPC分类号： H01L23/562 , H01L21/71 , H01L23/3114 , H01L24/05 , H01L2224/02379
摘要： Disclosed aspects include a semiconductor die including a substrate having a semiconductor surface including circuitry. A top metal layer is above the semiconductor surface including top metal lines that are electrically connected through a metal stack including metal interconnects that electrically connect to the circuitry. The top metal lines are configured in a primary orientation that collectively represents at least 50% of a total length of the top metal lines in a first direction. The top metal layer includes bond pads exposed from a passivation layer. The metal features are positioned lateral to and not directly electrically connected to the top metal layer and/or are positioned on the passivation layer. At least a majority of a total area of the metal features is not over metal interconnects. The metal features have a length direction oriented in a second direction that is at least essentially perpendicular relative to the primary orientation.
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公开(公告)号：US20230139898A1
公开(公告)日：2023-05-04
申请号：US17512958
申请日：2021-10-28
摘要： Disclosed aspects include a semiconductor die including a substrate having a semiconductor surface including circuitry. A top metal layer is above the semiconductor surface including top metal lines that are electrically connected through a metal stack including metal interconnects that electrically connect to the circuitry. The top metal lines are configured in a primary orientation that collectively represents at least 50% of a total length of the top metal lines in a first direction. The top metal layer includes bond pads exposed from a passivation layer. The metal features are positioned lateral to and not directly electrically connected to the top metal layer and/or are positioned on the passivation layer. At least a majority of a total area of the metal features is not over metal interconnects. The metal features have a length direction oriented in a second direction that is at least essentially perpendicular relative to the primary orientation.
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公开(公告)号：US20230137852A1
公开(公告)日：2023-05-04
申请号：US17515369
申请日：2021-10-29
IPC分类号： H01L23/495 , H01L23/00 , H01L21/48 , H01L21/56
摘要： In a described example, an apparatus includes: a package substrate for mounting a semiconductor die to a die side surface, the package substrate including leads spaced from one another; and cavities extending into the leads from the die side surface, the cavities having sides and a bottom surface of the lead material, the cavities at locations corresponding to post connect locations on the semiconductor die.
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公开(公告)号：US20220396474A1
公开(公告)日：2022-12-15
申请号：US17345707
申请日：2021-06-11
摘要： A semiconductor package includes a semiconductor die including terminals, a plurality of leads, at least some of the leads being electrically coupled to the terminals within the semiconductor package, a sensor on a surface of the semiconductor die, a set of metal columns on the surface of the semiconductor die, the set of metal columns forming a perimeter around the sensor on the surface of the semiconductor die, and a mold compound surrounding the semiconductor die except for an area inside the perimeter on the surface of the semiconductor die such that the sensor is exposed to ambient air.
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公开(公告)号：US11864471B2
公开(公告)日：2024-01-02
申请号：US17514820
申请日：2021-10-29
CPC分类号： H10N52/80 , G01R33/0011 , G01R33/07 , H10N50/85 , H10N52/01 , H10N52/101
摘要： A described example includes: a semiconductor die including a Hall sensor arranged in a first plane that is parallel to a device side surface of the semiconductor die; a passivated magnetic concentrator including a magnetic alloy layer formed over the device side surface of the semiconductor die, the upper surface of the magnetic alloy layer covered by a layer of polymer material; a backside surface of the semiconductor die opposite the device side surface mounted to a die side surface of a die pad on a package substrate, the semiconductor die having bond pads on the device side surface spaced from the magnetic concentrator; electrical connections coupling the bond pads of the semiconductor die to leads of the package substrate; and mold compound covering the magnetic concentrator, the semiconductor die, the electrical connections, a portion of the leads, and the die side surface of the die pad.
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公开(公告)号：US11699639B2
公开(公告)日：2023-07-11
申请号：US17219768
申请日：2021-03-31
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L23/4952 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/11552 , H01L2224/13011 , H01L2224/13564 , H01L2224/81815
摘要： In some examples, a quad flat no lead (QFN) semiconductor package comprises a flip chip semiconductor die having a surface and circuitry formed in the surface; and a conductive pillar coupled to the semiconductor die surface. The conductive pillar has a distal end relative to the semiconductor die, the distal end having a cavity including a cavity floor and one or more cavity walls circumscribing the cavity floor. The one or more cavity walls are configured to contain solder.
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公开(公告)号：US11637083B2
公开(公告)日：2023-04-25
申请号：US17219453
申请日：2021-03-31
摘要： In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.
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