公开(公告)号：US20180151725A1

公开(公告)日：2018-05-31

申请号：US15864865

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Zachary K. LEE

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/404 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

Abstract: An LDMOS device includes a handle portion having a buried dielectric layer and a semiconductor layer thereon doped a second dopant type. A drift region doped a first type is within the semiconductor layer providing a drain extension. A gate stack includes a gate electrode on a gate dielectric layer on respective sides of a junction with the drift region. A DWELL region is within the semiconductor layer. A source region doped the first type is within the DWELL region. A drain region doped the first type is within the drift region. A first partial buried layer doped the second type is in a first portion of the drift region including under the gate electrode. A second partial buried layer doped the first type is in a second portion of the drift region including under the drain.

公开(公告)号：US20160315159A1

公开(公告)日：2016-10-27

申请号：US15188110

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong YANG ,  Seetharaman SRIDHAR ,  Yufei XIONG ,  Yunlong LIU ,  Zachary K. LEE ,  Peng HU

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L21/288 ,  H01L29/08 ,  H01L29/732 ,  H01L21/285 ,  H01L29/45 ,  H01L29/423

CPC classification number: H01L29/41766 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/743 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material

Abstract translation: 一种具有低电阻沉降接触的半导体器件，其中低电阻沉降片接触被蚀刻穿过第一掺杂层并被蚀刻到第二掺杂层中，并且其中第一掺杂层覆盖在第二掺杂层上，并且其中第二掺杂层更重 掺杂了第一掺杂层，并且其中低电阻沉降片接触体填充有金属材料。 一种用于形成具有低电阻沉降接触的半导体器件的方法，其中所述低电阻沉降片接触被蚀刻通过第一掺杂层并且被蚀刻到第二掺杂层中，并且其中所述第一掺杂层覆盖所述第二掺杂层，并且其中所述第二掺杂 所述第一掺杂层更加重掺杂，并且其中所述低电阻沉降片接触体填充有金属材料