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    VERTICAL TRENCH GATE FET WITH SPLIT GATE
    2.
    发明申请
    VERTICAL TRENCH GATE FET WITH SPLIT GATE 有权

    公开(公告)号：US20220223731A1

    公开(公告)日：2022-07-14

    申请号：US17147875

    申请日：2021-01-13

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Sunglyong KIM ,  Seetharaman SRIDHAR ,  Meng-Chia LEE ,  Thomas Eugene GREBS ,  Hong YANG

    IPC分类号： H01L29/78 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

    摘要： A semiconductor device includes first, second and third trenches formed in a semiconductor layer having a first conductivity type. Each trench includes a corresponding field plate and a corresponding gate over each field plate. A first body region having a second opposite conductivity type is between the first and second gates, and a second body region having the second conductivity type is located between the second and third gates. A first source region is located over the first body region and a second source region is located over the second body region, the first and second source regions having the first conductivity type. A first gate bus is conductively connected to the first gate and a second gate bus is conductively connected to the second gate, the first gate bus conductively isolated from the second gate bus.

    TRENCH SHIELD ISOLATION LAYER
    3.
    发明申请
    TRENCH SHIELD ISOLATION LAYER 有权

    公开(公告)号：US20220208601A1

    公开(公告)日：2022-06-30

    申请号：US17695119

    申请日：2022-03-15

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Hong YANG ,  Seetharaman SRIDHAR ,  Ya ping CHEN ,  Fei MA ,  Yunlong LIU ,  Sunglyong KIM

    IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/324

    摘要： A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

    TRENCH SHIELD ISOLATION LAYER
    5.
    发明申请
    TRENCH SHIELD ISOLATION LAYER 审中-公开

    公开(公告)号：US20200312710A1

    公开(公告)日：2020-10-01

    申请号：US16546499

    申请日：2019-08-21

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Hong YANG ,  Seetharaman SRIDHAR ,  Ya ping CHEN ,  Fei MA ,  Yunlong LIU ,  Sunglyong KIM

    IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/324 ,  H01L21/308 ,  H01L21/02 ,  H01L29/66

    摘要： A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

    SEMICONDUCTOR PRODUCT AND FABRICATION PROCESS
    9.
    发明申请
    SEMICONDUCTOR PRODUCT AND FABRICATION PROCESS 审中-公开

    公开(公告)号：US20190157142A1

    公开(公告)日：2019-05-23

    申请号：US16241143

    申请日：2019-01-07

    申请人： Texas Instruments Incorporated

    发明人： Hong YANG ,  Abbas ALI ,  Yaping CHEN ,  Chao ZUO ,  Seetharaman SRIDHAR ,  Yunlong LIU

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L21/3213

    摘要： Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.