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公开(公告)号：US08819474B2
公开(公告)日：2014-08-26
申请号：US12417828
申请日：2009-04-03
IPC分类号： G06F1/12
CPC分类号： G06F13/4243 , G06F13/1689
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于存储器命令定时的主动训练的系统，方法和装置。 在一些实施例中，使用存储器模块和存储器控制器之间的主动反馈主动地训练CMD / CTL定时。 描述和要求保护其他实施例。
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公开(公告)号：US20100257397A1
公开(公告)日：2010-10-07
申请号：US12417828
申请日：2009-04-03
CPC分类号： G06F13/4243 , G06F13/1689
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于存储器命令定时的主动训练的系统，方法和装置。 在一些实施例中，使用存储器模块和存储器控制器之间的主动反馈主动地训练CMD / CTL定时。 描述和要求保护其他实施例。
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公开(公告)号：US08868992B2
公开(公告)日：2014-10-21
申请号：US12651252
申请日：2009-12-31
申请人： Bryan L. Spry , Theodore Z. Schoenborn , Philip Abraham , Christopher P. Mozak , David G. Ellis , Jay J. Nejedlo , Bruce Querbach , Zvika Greenfield , Rony Ghattas , Jayasekhar Tholiyil , Charles D. Lucas , Christopher E. Yunker
发明人： Bryan L. Spry , Theodore Z. Schoenborn , Philip Abraham , Christopher P. Mozak , David G. Ellis , Jay J. Nejedlo , Bruce Querbach , Zvika Greenfield , Rony Ghattas , Jayasekhar Tholiyil , Charles D. Lucas , Christopher E. Yunker
摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
摘要翻译： 引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。 此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。 还公开了地址图案生成电路。
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4.发明授权Method and system for evaluating effects of signal phase difference on a memory system 有权用于评估信号相位差对存储器系统的影响的方法和系统公开(公告)号：US08331176B2
公开(公告)日：2012-12-11
申请号：US12628103
申请日：2009-11-30
申请人： Christopher P. Mozak , Kevin B. Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Christopher E. Yunker
发明人： Christopher P. Mozak , Kevin B. Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Christopher E. Yunker
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/023 , G11C29/028
摘要： In an embodiment, the effect of signal phase difference on a memory system is tested for various operating states. The various operating states may be represented as respective sample points on a plane defined by a range of values for a difference in signal phases and a range of values for another operating state parameter. In various embodiments, sample points for a round of crosstalk testing may include two sample points which are offset from the same reference point on the plane along different respective axes, where the axes are oblique to one another.
摘要翻译： 在一个实施例中，针对各种操作状态测试信号相位差对存储器系统的影响。 各种操作状态可以被表示为由用于信号相位差和用于另一操作状态参数的值的范围的值的范围所限定的平面上的相应采样点。 在各种实施例中，用于一轮串扰测试的采样点可以包括两个采样点，这两个采样点沿着不同相应轴的平面上的相同参考点偏移，其中轴彼此倾斜。
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5.发明申请METHOD AND SYSTEM FOR EVALUATING EFFECTS OF SIGNAL PHASE DIFFERENCE ON A MEMORY SYSTEM 有权用于评估信号相位差对存储器系统的影响的方法和系统公开(公告)号：US20110131458A1
公开(公告)日：2011-06-02
申请号：US12628103
申请日：2009-11-30
申请人： Christopher P. Mozak , Kevin B. Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Christopher E. Yunker
发明人： Christopher P. Mozak , Kevin B. Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Christopher E. Yunker
CPC分类号： G11C29/02 , G11C29/023 , G11C29/028
摘要： In an embodiment, the effect of signal phase difference on a memory system is tested for various operating states. The various operating states may be represented as respective sample points on a plane defined by a range of values for a difference in signal phases and a range of values for another operating state parameter. In various embodiments, sample points for a round of crosstalk testing may include two sample points which are offset from the same reference point on the plane along different respective axes, where the axes are oblique to one another.
摘要翻译： 在一个实施例中，针对各种操作状态测试信号相位差对存储器系统的影响。 各种操作状态可以被表示为由用于信号相位差和用于另一操作状态参数的值的范围的值的范围所限定的平面上的相应采样点。 在各种实施例中，用于一轮串扰测试的采样点可以包括两个采样点，这两个采样点沿着不同相应轴的平面上的相同参考点偏移，其中轴彼此倾斜。
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公开(公告)号：US07886174B2
公开(公告)日：2011-02-08
申请号：US11769414
申请日：2007-06-27
CPC分类号： G06F13/1689
摘要： An apparatus and method are disclosed. In one embodiment, the apparatus trains a memory link using a signal alignment unit. The signal alignment unit aligns a read data strobe signal that is transmitted on the link with the center of a read data eye transmitted on the link. Next, the signal alignment unit aligns a receive enable signal that is transmitted on the link with the absolute time that data returns the data lines of the link a column address strobe signal is sent to the memory coupled to the link. Next, the signal alignment unit aligns a write data strobe signal transmitted on the link with the link's clock signal. Finally, the signal alignment unit aligns the center of the write data eye transmitted on the link with the write data strobe transmitted on the link.
摘要翻译： 公开了一种装置和方法。 在一个实施例中，该装置使用信号对准单元来训练存储器链路。 信号对准单元将在链路上发送的读数据选通信号与在链路上发送的读数据眼的中心对齐。 接下来，信号对准单元使在链路上发送的接收使能信号与数据将链路数据线的数据线返回给连接到链路的存储器的列地址选通信号发送的绝对时间对齐。 接下来，信号对准单元将在链路上发送的写数据选通信号与链路的时钟信号对齐。 最后，信号对准单元将在链路上发送的写入数据眼睛的中心与链路上发送的写数据选通脉冲对齐。
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公开(公告)号：US20090006776A1
公开(公告)日：2009-01-01
申请号：US11769414
申请日：2007-06-27
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： An apparatus and method are disclosed. In one embodiment, the apparatus trains a memory link using a signal alignment unit. The signal alignment unit aligns a read data strobe signal that is transmitted on the link with the center of a read data eye transmitted on the link. Next, the signal alignment unit aligns a receive enable signal that is transmitted on the link with the absolute time that data returns the data lines of the link a column address strobe signal is sent to the memory coupled to the link. Next, the signal alignment unit aligns a write data strobe signal transmitted on the link with the link's clock signal. Finally, the signal alignment unit aligns the center of the write data eye transmitted on the link with the write data strobe transmitted on the link.
摘要翻译： 公开了一种装置和方法。 在一个实施例中，该装置使用信号对准单元来训练存储器链路。 信号对准单元将在链路上发送的读数据选通信号与在链路上发送的读数据眼的中心对齐。 接下来，信号对准单元使在链路上发送的接收使能信号与数据将链路数据线的数据线返回给连接到链路的存储器的列地址选通信号发送的绝对时间对齐。 接下来，信号对准单元将在链路上发送的写数据选通信号与链路的时钟信号对齐。 最后，信号对准单元将在链路上发送的写入数据眼睛的中心与链路上发送的写数据选通脉冲对齐。
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8.发明申请METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM 有权用于动态调整电压参考以优化I / O系统的方法和装置公开(公告)号：US20110141827A1
公开(公告)日：2011-06-16
申请号：US12638887
申请日：2009-12-15
申请人： Christopher Mozak , Kevin Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Chris Yunker
发明人： Christopher Mozak , Kevin Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Chris Yunker
IPC分类号： G11C5/14
CPC分类号： G11C11/4091 , G11C5/147 , G11C11/4074 , G11C11/4093 , G11C11/4099
摘要： Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.
摘要翻译： 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括：电压基准发生器，用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元，以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法，包括：产生用于输入/输出（I / O）系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平，通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。
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9.发明授权Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system 有权用于动态调整电压参考以优化I / O系统的方法和装置公开(公告)号：US08582374B2
公开(公告)日：2013-11-12
申请号：US12638887
申请日：2009-12-15
申请人： Christopher Mozak , Kevin Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Chris Yunker
发明人： Christopher Mozak , Kevin Moore , John V. Lovelace , Zale Theodore Schoenborn , Bryan L. Spry , Chris Yunker
IPC分类号： G11C5/14
CPC分类号： G11C11/4091 , G11C5/147 , G11C11/4074 , G11C11/4093 , G11C11/4099
摘要： Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.
摘要翻译： 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括：电压基准发生器，用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元，以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法，包括：产生用于输入/输出（I / O）系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平，通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。
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10.发明授权公开(公告)号：US09734116B2
公开(公告)日：2017-08-15
申请号：US14658021
申请日：2015-03-13
申请人： Bryan L. Spry , Marcus W. Song , Deepak M. Rangaraj , Avinash N. Ananthakrishnan , Robert J. Hayes , Aimee D. Wood , Adam E. Letendre , Brent R. Boswell
发明人： Bryan L. Spry , Marcus W. Song , Deepak M. Rangaraj , Avinash N. Ananthakrishnan , Robert J. Hayes , Aimee D. Wood , Adam E. Letendre , Brent R. Boswell
CPC分类号： G06F13/4221 , G06F13/122 , G06F13/4265 , Y02D10/14 , Y02D10/151
摘要： Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
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