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公开(公告)号：US08451018B2
公开(公告)日：2013-05-28
申请号：US12706228
申请日：2010-02-16
申请人： Thomas D. Furland , Robert J. Milne, Jr. , Leah M. P. Pastel , Kevin W. Stanley , Robert C. Virun
发明人： Thomas D. Furland , Robert J. Milne, Jr. , Leah M. P. Pastel , Kevin W. Stanley , Robert C. Virun
IPC分类号： G01R31/26
CPC分类号： G01R31/31703 , G01R31/31935
摘要： A method, system, and program product for identifying at least one bit failure among a plurality of semiconductor chips are provided. A first aspect of the invention provides a method of identifying at least one bit failure signature among a plurality of semiconductor chips, the method comprising: counting failures of each failing bit among the plurality of semiconductor chips; determining a most commonly failing bit (MCFB) among the failing bits; establishing a bit failure signature including the MCFB; counting failures of each failing bit on semiconductor chips on which the MCFB fails; determining a next most commonly failing bit (NMCFB) among the failing bits on semiconductor chips on which the MCFB fails; determining whether the NMCFB tends to fail when the MCFB fails; and in response to a determination that the NMCFB tends to fail when the MCFB fails, adding the NMCFB to the bit failure signature.
摘要翻译： 提供了用于识别多个半导体芯片中的至少一个位故障的方法，系统和程序产品。 本发明的第一方面提供了一种识别多个半导体芯片中的至少一个位故障签名的方法，所述方法包括：对所述多个半导体芯片中的每个故障位进行计数故障; 确定故障位中最常见的故障位（MCFB）; 建立包括MCFB在内的位故障签名; 在MCFB故障的半导体芯片上的每个故障位的计数失败; 确定在MCFB故障的半导体芯片上的故障位中的下一个最常故障位（NMCFB）; 确定当MCFB发生故障时，NMCFB是否会失败; 并且响应于当MCFB失败时NMCFB趋向于失败的确定，将NMCFB添加到位故障签名。
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公开(公告)号：US07202689B2
公开(公告)日：2007-04-10
申请号：US10907787
申请日：2005-04-15
IPC分类号： G01R31/02
CPC分类号： G01R31/311 , G01R31/302 , G01R31/31728 , G01R31/3187
摘要： Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.
摘要翻译： 公开了一种用于诊断测试设备内的电路的装置和方法。 该装置和方法包括直接应用于设备上可能影响被测电路内的电活动的任何位置的能量（例如光，热，磁，电等）的使用，以便产生一个 响应。 本地传感器（例如，光子，磁性等）位于设备上的另一位置处，其中传感器可以检测电路内的响应的指示符。 相关器配置有响应位置相关软件和/或电路跟踪软件，使得当检测到指示符时，相关器可基于导致设备故障的确定位置和/或跟踪电路的连通性来确定电路的连接性 能源的位置和传感器的位置。
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3.发明授权Designing scan chains with specific parameter sensitivities to identify process defects 失效设计具有特定参数灵敏度的扫描链，以识别过程缺陷公开(公告)号：US07194706B2
公开(公告)日：2007-03-20
申请号：US10710642
申请日：2004-07-27
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Leendert M. Huisman , Mark D. Jaffe , Phillip J. Nigh , Leah M. P. Pastel , Thomas G. Sopchak , David E. Sweenor , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译： 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。
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公开(公告)号：US08015514B2
公开(公告)日：2011-09-06
申请号：US12344725
申请日：2008-12-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/66 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.
摘要翻译： 公开了用于在制造期间随机个性化芯片的方法的实施例，个性化芯片结构和用于这种个性化芯片结构的设计结构。 实施例使用电子设备设计和制造过程来随机地或伪随机地在每个芯片上形成的特定电子设备的一个或多个实例中创建特定变化。 调整设备设计和制造过程，使得特定变化以某种预定概率发生，从而产生期望的硬件分布和个性化每个芯片。 所得到的个性化芯片可用于芯片的模态分配。 例如，当单芯片设计可用于支持多种应用时，芯片可以被个性化以允许排序。 所产生的个性化芯片也可以用于随机数生成，用于创建唯一的片上标识符，私钥等。
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公开(公告)号：US07239167B2
公开(公告)日：2007-07-03
申请号：US11382601
申请日：2006-05-10
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译： 公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。 屏蔽与时钟信号接线相邻，接地线将屏蔽接地。 屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。 本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。
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公开(公告)号：US07139950B2
公开(公告)日：2006-11-21
申请号：US10707957
申请日：2004-01-28
CPC分类号： G01R31/318536
摘要： A method is disclosed of diagnosing defects in scan chains by statically and dynamically segmenting and reconfiguring the scan chains. A plurality of serially extending scan chains are partitioned into a plurality of serially arranged equal length segments such that each serially extending scan chain comprises a plurality of serially extending segments. A plurality of multiplexors are positioned between the plurality of segments of each scan chain, and are controlled and utilized to connect each segment of the scan chain to the next serial segment in the same scan chain, or to connect each segment of the scan chain to the next serial segment in a lateral adjacent scan chain. Scan in data patterns are introduced into the plurality of serially extending scan chains. Particular defective segments of the plurality of serially extending scan chains are identified by controlling the multiplexors to connect and shift the data pattern out of each segment of a scan chain serially to the next serial segment in the same scan chain, or to connect and shift the data pattern out of each segment of the scan chain to the next serial segment in an adjacent lateral scan chain, with a sequence of serial shifts and serial-lateral shifts being selected to identify particular defective segments of the plurality of serially extending scan chains.
摘要翻译： 公开了通过静态和动态地分割和重新配置扫描链来诊断扫描链中的缺陷的方法。 多个串联延伸的扫描链被分割成多个串联布置的等长段，使得每个连续延伸的扫描链包括多个串联延伸段。 多个多路复用器位于每个扫描链的多个段之间，并且被控制并用于将扫描链的每个段连接到相同扫描链中的下一个串行段，或将扫描链的每个段连接到 横向相邻扫描链中的下一个串行段。 扫描数据模式被引入到多个连续延伸的扫描链中。 通过控制多路复用器将扫描链的每个段中的数据模式串联连接并移动到同一扫描链中的下一个串行段来识别多个串行延伸扫描链中的特定缺陷段，或者将数据模式连接和移位 扫描链的每个段中的数据模式到相邻横向扫描链中的下一个串行段，其中选择串行移位和串行 - 横向移位序列以识别多个连续延伸扫描链中的特定缺陷段。
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公开(公告)号：US07089514B2
公开(公告)日：2006-08-08
申请号：US10710879
申请日：2004-08-10
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译： 一种半导体芯片缺陷诊断方法。 该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。
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公开(公告)号：US07247877B2
公开(公告)日：2007-07-24
申请号：US10711083
申请日：2004-08-20
IPC分类号： H01L31/072 , H01L23/48
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译： 一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。 此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。 此外，CNT FET适用于检测集成电路内的故障电路。
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公开(公告)号：US07005874B2
公开(公告)日：2006-02-28
申请号：US10710222
申请日：2004-06-28
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译： 公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。 屏蔽与时钟信号接线相邻，接地线将屏蔽接地。 屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。 本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。
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公开(公告)号：US06880136B2
公开(公告)日：2005-04-12
申请号：US10191212
申请日：2002-07-09
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.
摘要翻译： 通过使用LSSD技术的结果测试设备的缺陷来分析IC器件制造中的缺陷，以找到至少一个包含不正确值的故障模式。 使用故障锁存器作为起始点，通过组合逻辑来跟踪故障锁存器，直到遇到可控制的锁存器。 然后，决定是否在应用其中一种失败模式的情况下是否继续后跟踪。
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