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公开(公告)号：US08015514B2
公开(公告)日：2011-09-06
申请号：US12344725
申请日：2008-12-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/66 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.
摘要翻译： 公开了用于在制造期间随机个性化芯片的方法的实施例，个性化芯片结构和用于这种个性化芯片结构的设计结构。 实施例使用电子设备设计和制造过程来随机地或伪随机地在每个芯片上形成的特定电子设备的一个或多个实例中创建特定变化。 调整设备设计和制造过程，使得特定变化以某种预定概率发生，从而产生期望的硬件分布和个性化每个芯片。 所得到的个性化芯片可用于芯片的模态分配。 例如，当单芯片设计可用于支持多种应用时，芯片可以被个性化以允许排序。 所产生的个性化芯片也可以用于随机数生成，用于创建唯一的片上标识符，私钥等。
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公开(公告)号：US20100164013A1
公开(公告)日：2010-07-01
申请号：US12344725
申请日：2008-12-29
IPC分类号： H01L27/088 , H01L21/66 , G06F17/50
CPC分类号： G06F17/5068 , G06F2217/66 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.
摘要翻译： 公开了用于在制造期间随机个性化芯片的方法的实施例，个性化芯片结构和用于这种个性化芯片结构的设计结构。 实施例使用电子设备设计和制造过程来随机地或伪随机地在每个芯片上形成的特定电子设备的一个或多个实例中创建特定变化。 调整设备设计和制造过程，使得特定变化以某种预定概率发生，从而产生期望的硬件分布和个性化每个芯片。 所得到的个性化芯片可用于芯片的模态分配。 例如，当单芯片设计可用于支持多种应用时，芯片可以被个性化以允许排序。 所产生的个性化芯片也可以用于随机数生成，用于创建唯一的片上标识符，私钥等。
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公开(公告)号：US20100279480A1
公开(公告)日：2010-11-04
申请号：US12028847
申请日：2008-02-11
申请人： James William Adkisson , James Peter Gambino , Robert Kenneth Leidy , Walter Victor Lepuschenko , David Alan Meatyard , Stephen A. Mongeon , Richard John Rassel
发明人： James William Adkisson , James Peter Gambino , Robert Kenneth Leidy , Walter Victor Lepuschenko , David Alan Meatyard , Stephen A. Mongeon , Richard John Rassel
IPC分类号： H01L21/336 , H01L21/311 , H01L21/283
CPC分类号： H01L21/76843 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L21/76838 , H01L21/76885 , H01L29/51 , H01L29/6659 , H01L29/7833
摘要： A method of forming a small geometry feature. The method includes forming a source layer on a top surface of a substrate; forming a mandrel on a top surface of the source layer, the mandrel having a sidewall; sputtering material from the source layer onto the sidewall of the mandrel to form a sidewall layer on the sidewall of the mandrel; and removing the mandrel. Also methods to forming wires and field effect transistors of integrated circuits.
摘要翻译： 形成小几何特征的方法。 该方法包括在基板的顶表面上形成源层; 在所述源层的顶表面上形成心轴，所述心轴具有侧壁; 将来自源层的材料溅射到心轴的侧壁上以在心轴的侧壁上形成侧壁层; 并移除心轴。 还有形成集成电路的导线和场效应晶体管的方法。
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公开(公告)号：US20120138436A1
公开(公告)日：2012-06-07
申请号：US12961047
申请日：2010-12-06
CPC分类号： H01H59/0009 , B81B2201/014 , B81B2203/051 , B81C1/00293 , B81C2203/0145 , H01H2001/0052 , H01H2059/0027
摘要： MEMS switches and methods of fabricating MEMS switches. The switch has a vertically oriented deflection electrode having a conductive layer supported by a supporting layer, at least one drive electrode, and a stationary electrode. An actuation voltage applied to the drive electrode causes the deflection electrode to be deflect laterally and contact the stationary electrode, which closes the switch. The deflection electrode is restored to a vertical position when the actuation voltage is removed, thereby opening the switch. The method of fabricating the MEMS switch includes depositing a conductive layer on mandrels to define vertical electrodes and then releasing the deflection electrode by removing the mandrel and layer end sections.
摘要翻译： MEMS开关和制造MEMS开关的方法。 开关具有垂直取向的偏转电极，其具有由支撑层支撑的导电层，至少一个驱动电极和固定电极。 施加到驱动电极的致动电压使得偏转电极横向偏转并且接触固定电极，该固定电极闭合开关。 当去除致动电压时，偏转电极恢复到垂直位置，从而打开开关。 制造MEMS开关的方法包括在心轴上沉积导电层以限定垂直电极，然后通过去除心轴和层端部来释放偏转电极。
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公开(公告)号：US6028339A
公开(公告)日：2000-02-22
申请号：US211565
申请日：1998-12-14
申请人： Robert O. Frenette , Dale P. Hallock , Stephen A. Mongeon , Anthony C. Speranza , William R. P. Tonti
发明人： Robert O. Frenette , Dale P. Hallock , Stephen A. Mongeon , Anthony C. Speranza , William R. P. Tonti
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823842 , Y10S257/90
摘要： A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.
摘要翻译： 公开了一种双功能功能CMOS器件及其制造方法。 该方法包括：在要掺杂的衬底上沉积n型或p型掺杂材料的第一层; 定义要相反掺杂的区域; 在整个表面上沉积相对掺杂的材料的第二层; 并对整个CMOS器件进行高温，驱动退火。 驱动退火加速了掺杂剂进入相邻区域的扩散，从而掺杂了所需掺杂剂的栅极多晶硅和沟道。 可以使用氮化物阻挡层来防止第二掺杂剂通过第一层扩散到下面的衬底中。
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公开(公告)号：US08609450B2
公开(公告)日：2013-12-17
申请号：US12961047
申请日：2010-12-06
IPC分类号： H01L21/00
CPC分类号： H01H59/0009 , B81B2201/014 , B81B2203/051 , B81C1/00293 , B81C2203/0145 , H01H2001/0052 , H01H2059/0027
摘要： MEMS switches and methods of fabricating MEMS switches. The switch has a vertically oriented deflection electrode having a conductive layer supported by a supporting layer, at least one drive electrode, and a stationary electrode. An actuation voltage applied to the drive electrode causes the deflection electrode to be deflect laterally and contact the stationary electrode, which closes the switch. The deflection electrode is restored to a vertical position when the actuation voltage is removed, thereby opening the switch. The method of fabricating the MEMS switch includes depositing a conductive layer on mandrels to define vertical electrodes and then releasing the deflection electrode by removing the mandrel and layer end sections.
摘要翻译： MEMS开关和制造MEMS开关的方法。 开关具有垂直取向的偏转电极，其具有由支撑层支撑的导电层，至少一个驱动电极和固定电极。 施加到驱动电极的致动电压使得偏转电极横向偏转并且接触固定电极，该固定电极闭合开关。 当去除致动电压时，偏转电极恢复到垂直位置，从而打开开关。 制造MEMS开关的方法包括在心轴上沉积导电层以限定垂直电极，然后通过去除心轴和层端部来释放偏转电极。
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公开(公告)号：US07935604B2
公开(公告)日：2011-05-03
申请号：US12028847
申请日：2008-02-11
申请人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , Walter Victor Lepuschenko , David Alan Meatyard , Stephen A. Mongeon , Richard John Rassel
发明人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , Walter Victor Lepuschenko , David Alan Meatyard , Stephen A. Mongeon , Richard John Rassel
IPC分类号： H01L21/336
CPC分类号： H01L21/76843 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L21/76838 , H01L21/76885 , H01L29/51 , H01L29/6659 , H01L29/7833
摘要： A method of forming a small geometry feature. The method includes forming a source layer on a top surface of a substrate; forming a mandrel on a top surface of the source layer, the mandrel having a sidewall; sputtering material from the source layer onto the sidewall of the mandrel to form a sidewall layer on the sidewall of the mandrel; and removing the mandrel. Also methods to forming wires and field effect transistors of integrated circuits.
摘要翻译： 形成小几何特征的方法。 该方法包括在基板的顶表面上形成源层; 在所述源层的顶表面上形成心轴，所述心轴具有侧壁; 将来自源层的材料溅射到心轴的侧壁上以在心轴的侧壁上形成侧壁层; 并移除心轴。 还有形成集成电路的导线和场效应晶体管的方法。
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公开(公告)号：US5770490A
公开(公告)日：1998-06-23
申请号：US705579
申请日：1996-08-29
申请人： Robert O. Frenette , Dale P. Hallock , Stephen A. Mongeon , Anthony C. Speranza , William R. P. Tonti
发明人： Robert O. Frenette , Dale P. Hallock , Stephen A. Mongeon , Anthony C. Speranza , William R. P. Tonti
IPC分类号： H01L21/28 , H01L21/8238
CPC分类号： H01L21/28035 , H01L21/823842
摘要： A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.
摘要翻译： 公开了一种双功能功能CMOS器件及其制造方法。 该方法包括：在要掺杂的衬底上沉积n型或p型掺杂材料的第一层; 定义要相反掺杂的区域; 在整个表面上沉积相对掺杂的材料的第二层; 并对整个CMOS器件进行高温，驱动退火。 驱动退火加速了掺杂剂进入相邻区域的扩散，从而掺杂了所需掺杂剂的栅极多晶硅和沟道。 可以使用氮化物阻挡层来防止第二掺杂剂通过第一层扩散到下面的衬底中。
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9.发明授权Method of making a diffused lightly doped drain device with built in etch stop 失效制造具有内置蚀刻停止点的扩散轻掺杂漏极器件的方法
公开(公告)号：US5518945A
公开(公告)日：1996-05-21
申请号：US435262
申请日：1995-05-05
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/823864 , H01L29/6656 , Y10S148/144 , Y10S438/975
摘要： A method of fabricating a lightly doped drain MOSFET device with a built in etch stop is disclosed. After forming a gate electrode on a substrate through conventional methods, a conformal doped layer is deposited on the gate electrode. A conformal layer of nitride is then deposited on the conformal doped layer. The nitride layer is etched, with the etch stopping on the conformal doped layer, thereby forming nitride spacers. Deep source and drain regions are formed by either ion implantation or diffusion. The device is then heat treated so that light diffusion occurs under the nitride spacers and heavy diffusion occurs outside the spacer region. The method is applicable to N-substrate (P-channel), P-substrate (N-channel), and complementary metal oxide semiconductor (CMOS) devices.
摘要翻译： 公开了一种制造具有内置蚀刻停止层的轻掺杂漏极MOSFET器件的方法。 在通过常规方法在衬底上形成栅电极之后，在栅电极上沉积共形掺杂层。 然后在共形掺杂层上沉积氮化物共形层。 蚀刻氮化物层，在保形掺杂层上停止蚀刻，从而形成氮化物间隔物。 通过离子注入或扩散形成深源极和漏极区。 然后对该器件进行热处理，使得在氮化物间隔物下发生光扩散，并且在间隔区外部发生重度扩散。 该方法适用于N衬底（P沟道），P衬底（N沟道）和互补金属氧化物半导体（CMOS）器件。
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