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    Dynamic delay or advance adjustment of oscillating signal phase
    2.
    发明授权
    Dynamic delay or advance adjustment of oscillating signal phase 有权
    振荡信号相位的动态延迟或提前调整

    公开(公告)号：US07586344B1

    公开(公告)日：2009-09-08

    申请号：US11872950

    申请日：2007-10-16

    申请人： Richard Booth ,  Phillip Johnson ,  Zheng Chen

    发明人： Richard Booth ,  Phillip Johnson ,  Zheng Chen

    IPC分类号： H03B19/00

    CPC分类号： G06F1/06 ,  H03K21/406

    摘要： In one embodiment, the invention can be a clock-generating circuit having one or more clock-processing circuits, each outputting a clock signal having an adjustable phase. Each clock-processing circuit comprises a divider and a divisor control circuit. Each divider divides an input clock signal by a respective divisor value and outputs a corresponding output clock signal whose period is determined by the divisor value and the period of the input clock signal. Each divider receives the respective divisor value from the corresponding divisor control circuit, wherein the divisor value is selected in order to achieve a desired frequency and phase for the corresponding output clock signal. Temporarily changing a divisor value can advance or delay the phase of the corresponding output clock signal without having to reset the divider.

    摘要翻译： 在一个实施例中，本发明可以是具有一个或多个时钟处理电路的时钟发生电路，每个时钟处理电路输出具有可调相位的时钟信号。 每个时钟处理电路包括除法器和除数控制电路。 每个除法器将输入时钟信号除以相应的除数值，并输出相应的输出时钟信号，其周期由除数值和输入时钟信号的周期确定。 每个分频器从相应的除数控制电路接收相应的除数值，其中选择除数值以便为相应的输出时钟信号实现期望的频率和相位。 临时改变除数值可以提前或延迟对应的输出时钟信号的相位，而不必复位分频器。

    Jitter tolerant delay-locked loop circuit
    3.
    发明申请
    Jitter tolerant delay-locked loop circuit 有权
    抖动容限延迟锁定环路

    公开(公告)号：US20070136619A1

    公开(公告)日：2007-06-14

    申请号：US11302097

    申请日：2005-12-13

    申请人： Zheng (Jeff) Chen ,  Phillip Johnson ,  Fulong Zhang

    发明人： Zheng (Jeff) Chen ,  Phillip Johnson ,  Fulong Zhang

    IPC分类号： G06F1/00

    CPC分类号： G06F1/04 ,  G06F1/12

    摘要： Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.

    摘要翻译： 本文公开了系统和方法以提供改进的抖动容限延迟锁定环路。 例如，根据本发明的实施例，集成电路包括多个延迟单元，每个延迟单元具有多个可编程延迟抽头。 每个延迟单元适于提供延迟选定数量的延迟抽头的延迟时钟信号。 相位检测器适于将第一时钟信号与所选延迟时钟信号中的一个进行比较，以获得比较结果，并响应于比较结果提供多个​​控制信号。 算术逻辑单元（ALU）适于响应于由相位检测器提供的控制信号来改变选定数量的延迟抽头。

    Bandgap generator providing low-voltage operation
    4.
    发明申请
    Bandgap generator providing low-voltage operation 审中-公开
    带隙发生器提供低电压工作

    公开(公告)号：US20060261882A1

    公开(公告)日：2006-11-23

    申请号：US11131053

    申请日：2005-05-17

    申请人： Phillip Johnson

    发明人： Phillip Johnson

    IPC分类号： G05F1/10

    CPC分类号： G05F3/30

    摘要： A bandgap reference circuit uses a pair of parallel loads and an op-amp driver circuit. The op-amp driver circuit uses NMOS inputs to sense voltage conditions at the loads. The configuration permits low-voltage response at low temperatures as a result of the configuration setting operating voltages above a saturation voltage. The op-amp driver provides an NMOS output, and a low-gain stage converts the NMOS output to an output corresponding to that of a conventional PMOS design.

    摘要翻译： 带隙参考电路使用一对并联负载和运放驱动电路。 运放驱动电路使用NMOS输入来检测负载下的电压状况。 由于配置设置工作电压高于饱和电压，配置允许低温下的低电压响应。 运算放大器驱动器提供NMOS输出，低增益级将NMOS输出转换为与传统PMOS设计相对应的输出。

    Noise-shielding, switch-controlled load circuitry for oscillators and the like
    5.
    发明授权
    Noise-shielding, switch-controlled load circuitry for oscillators and the like 有权
    用于振荡器的噪声屏蔽，开关控制负载电路等

    公开(公告)号：US07132903B1

    公开(公告)日：2006-11-07

    申请号：US10613460

    申请日：2003-07-03

    申请人： Phillip Johnson ,  Gary Powell ,  Harold Scholz

    发明人： Phillip Johnson ,  Gary Powell ,  Harold Scholz

    IPC分类号： H03L1/00 ,  H03B27/00

    CPC分类号： H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03L7/0812 ,  H03L7/0995

    摘要： A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.

    摘要翻译： 一组互连的延迟级，例如压控振荡器，具有连接到振荡器环中每个延迟级的每个输出的开关控制负载电路。 在一个实施例中，对于每个延迟级输出，开关控制的负载电路包括开关，晶体管和电流源。 开关连接在相应的延迟级输出和晶体管栅极之间，电流源连接在电源和晶体管漏极之间，晶体管源连接到地。 在这种配置中，例如，对于较低频率的操作，晶体管的栅极 - 源极电容可以被施加到相应的延迟级输出。 此外，电流源的输出阻抗使电容负载与电源分离，从而基本上屏蔽振荡器环免受电源中的噪声。

    Discrete time digital phase locked loop
    6.
    发明授权
    Discrete time digital phase locked loop 失效
    离散时间数字锁相环

    公开(公告)号：US5576664A

    公开(公告)日：1996-11-19

    申请号：US556882

    申请日：1995-11-02

    申请人： Barry W. Herold ,  Scott R. Humphreys ,  Phillip Johnson ,  Raymond L. Barrett, Jr. ,  Grazyna A. Pajunen

    发明人： Barry W. Herold ,  Scott R. Humphreys ,  Phillip Johnson ,  Raymond L. Barrett, Jr. ,  Grazyna A. Pajunen

    IPC分类号： H03L7/091 ,  H03L7/093 ,  H03L7/181

    CPC分类号： H03L7/091 ,  H03L7/093 ,  H03L7/181

    摘要： A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).

    摘要翻译： 通信接收器（100）采用离散时间数字锁相环（142）来保持锁定到参考信号（136）的生成信号（144）。 离散时间数字锁相环（142）包括相位检测器（202），累加器（219），加法器（227）和受控振荡器（232）。 累加器（219）连接到相位检测器（202）和参考信号（136），用于计算等于由相位检测器（202）生成的当前采样的第一和的累加器输出值，并且所有多个 在当前样本之前产生的离散相位误差样本。 加法器（227）连接到相位检测器（202）和累加器（219），用于形成当前采样和累加器输出值的第二和。 受控振荡器（232）接收用于控制受控振荡器（232）的第二和。

    Card game
    7.
    发明授权
    Card game 失效
    纸牌游戏

    公开(公告)号：US5573249A

    公开(公告)日：1996-11-12

    申请号：US296441

    申请日：1994-08-26

    申请人： Phillip Johnson

    发明人： Phillip Johnson

    IPC分类号： A63F1/00 ,  A63F3/00 ,  G07F17/32

    CPC分类号： G07F17/32 ,  A63F3/00157 ,  A63F2001/008 ,  A63F2250/142

    摘要： Method for playing a card game comprising the steps of providing at least one player with an opportunity to place a wager, displaying a first plurality of playing card indicia to form a plurality of partial card hands, allowing the player to assign the wager to one of the plurality of partial card hands, and subsequently completing the card hands by displaying an additional plurality of card indicia. When the hands have been completed, a winning payout is provided to any and all players who successfully assigned their wagers to the partial card hand which resulted in the complete hand having a particular value, e.g. the highest poker ranking.

    摘要翻译： 用于玩纸牌游戏的方法包括以下步骤：向至少一个玩家提供放置下注的机会，显示第一多个扑克牌标记以形成多个部分牌手，允许玩家将赌注分配给 多个部分卡牌手，并且随后通过显示附加的多个卡片标记来完成卡牌手。 当手已经完成时，向成功地将他们的下注分配给部分卡牌手的任何和所有玩家提供获胜奖金，这导致完整的手具有特定价值，例如。 扑克排名最高。

    Programmable lock detector and corrector
    10.
    发明授权
    Programmable lock detector and corrector 有权
    可编程锁定检测器和校正器

    公开(公告)号：US06970047B1

    公开(公告)日：2005-11-29

    申请号：US10628656

    申请日：2003-07-28

    申请人： Phillip Johnson ,  Gary Powell ,  William Andrews

    发明人： Phillip Johnson ,  Gary Powell ,  William Andrews

    IPC分类号： H03K5/13 ,  H03K5/15 ,  H03L7/081 ,  H03L7/095 ,  H03L7/10

    CPC分类号： H03L7/0814 ,  H03K5/15013 ,  H03L7/095 ,  H03L7/10 ,  Y10S331/02

    摘要： An apparatus and method for programmable lock detection and correction (PLDC) to a programmable accuracy in a digital delay-locked loop (DLL) based multiphase clock generator (MCG) is based on a DLL that utilizes a digital count to control the delay of a digitally controlled, multiple-tap delay line in its feedback path where stability of the digital count is used to qualify the determination of lock to a programmable accuracy and lock determination is based on combinatorial evaluation of the multiple phase outputs for the proper waveform relationships. The incidence of false lock corresponding to excessive delay through the delay line is addressed by a LOOPRESET signal that results in a reset of the digital count that controls the delay through the delay line. Additionally, programmability of the stability interval, the digital counter step size, and the accuracy of the lock provide control over lock acquisition time.

    摘要翻译： 基于数字延迟锁定环（DLL）的多相时钟发生器（MCG）中的可编程锁定检测和校正（PLDC）的装置和方法，其基于利用数字计数来控制延迟锁定环 在其反馈路径中的数字控制的多抽头延迟线，其中使用数字计数的稳定性来将锁定的确定限定到可编程精度和锁定确定，基于用于适当波形关系的多相输出的组合评估。 通过延迟线对应于过度延迟的假锁的发生率由LOOPRESET信号来解决，该LOOPRESET信号导致数字计数的复位，该数字计数通过延迟线控制延迟。 此外，稳定性间隔的可编程性，数字计数器步长和锁的精度提供了对锁获取时间的控制。