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    Dual port memory, such as used in color lookup tables for video systems
    1.
    发明授权
    Dual port memory, such as used in color lookup tables for video systems 失效
    双端口存储器，例如用于视频系统的颜色查找表

    公开(公告)号：US5576560A

    公开(公告)日：1996-11-19

    申请号：US267036

    申请日：1994-06-27

    申请人： Thomas J. Runaldue ,  William Plants

    发明人： Thomas J. Runaldue ,  William Plants

    IPC分类号： G09G5/00 ,  G06T1/20 ,  G06T1/60 ,  G09G5/06 ,  G11C7/10 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/10

    CPC分类号： H01L27/1104 ,  G09G5/06 ,  G11C7/1075 ,  Y10S257/903

    摘要： An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory.Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal. A second transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a bit line of the video path, and a gate coupled to a word line of the video path.A layout configuration of each memory cell and of the memory cell array allows same-channel-type transistors from a plurality of memory cells to be formed in a single, large well, and allows adjacent memory cells to share contacts. This reduces the integrated circuit's size, improves its speed, and increases manufacturing yields.

    摘要翻译： 一种用于显示系统的颜色查找表的集成电路存储器。 存储器具有视频端口和路径，用于读取识别> 100或甚至> 200兆比特的像素的颜色的数据，以及用于读取和写入识别存储器中的位置处的颜色的数据的CPU端口和路径。 每个存储单元包括具有真和补码端子的触发器。 CPU端口包括两个通过晶体管，每个具有耦合到真实或补充端子的第一通道端子，耦合到CPU路径的双向位线的第二通道端子以及耦合到CPU路径的字线的栅极。 视频端口包括隔离的感测端子和两个晶体管。 第一晶体管具有耦合到隔离感测端子的第一通道端子，耦合到参考电压的第二通道端子和耦合到真或补体端子的栅极。 第二晶体管具有耦合到隔离感测端子的第一通道端子，耦合到视频通路的位线的第二通道端子和耦合到视频通路的字线的栅极。 每个存储单元和存储单元阵列的布局配置允许在单个大的阱中形成来自多个存储单元的相同通道型晶体管，并允许相邻的存储单元共享触点。 这降低了集成电路的尺寸，提高了其速度，并提高了制造成品率。

    Dual port memory, such as used in color lookup tables for video systems
    2.
    发明授权
    Dual port memory, such as used in color lookup tables for video systems 失效
    双端口存储器，例如用于视频系统的颜色查找表

    公开(公告)号：US5325338A

    公开(公告)日：1994-06-28

    申请号：US754910

    申请日：1991-09-04

    申请人： Thomas J. Runaldue ,  William Plants

    发明人： Thomas J. Runaldue ,  William Plants

    IPC分类号： G09G5/00 ,  G06T1/20 ,  G06T1/60 ,  G09G5/06 ,  G11C7/10 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00 ,  G09G1/28

    CPC分类号： H01L27/1104 ,  G09G5/06 ,  G11C7/1075 ,  Y10S257/903

    摘要： An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory. Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal. A second transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a bit line of the video path, and a gate coupled to a word line of the video path.

    摘要翻译： 一种用于显示系统的颜色查找表的集成电路存储器。 存储器具有视频端口和路径，用于读取识别> 100或甚至> 200兆比特的像素的颜色的数据，以及用于读取和写入识别存储器中的位置处的颜色的数据的CPU端口和路径。 每个存储单元包括具有真和补码端子的触发器。 CPU端口包括两个通过晶体管，每个具有耦合到真实或补充端子的第一通道端子，耦合到CPU路径的双向位线的第二通道端子以及耦合到CPU路径的字线的栅极。 视频端口包括隔离的感测端子和两个晶体管。 第一晶体管具有耦合到隔离感测端子的第一通道端子，耦合到参考电压的第二通道端子和耦合到真或补体端子的栅极。 第二晶体管具有耦合到隔离感测端子的第一通道端子，耦合到视频通路的位线的第二通道端子和耦合到视频通路的字线的栅极。

    Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
    3.
    发明申请
    Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array 失效
    辐射硬化静态随机存取存储器现场可编程门阵列中误差检测和校正的装置和方法

    公开(公告)号：US20060145722A1

    公开(公告)日：2006-07-06

    申请号：US11367081

    申请日：2006-03-02

    申请人： William Plants

    发明人： William Plants

    IPC分类号： H03K19/007

    CPC分类号： G06F11/1008 ,  G11C5/005 ,  G11C11/4125 ,  H01L27/118 ,  H03K19/00338 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

    摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).

    摘要翻译： 本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。 提供配置数据的配置数据线控制逻辑模块和路由资源的编程。 耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。

    SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA
    4.
    发明申请
    SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA 失效
    SRAM总线架构和与FPGA的连接

    公开(公告)号：US20070182600A1

    公开(公告)日：2007-08-09

    申请号：US11688688

    申请日：2007-03-20

    申请人： William Plants

    发明人： William Plants

    IPC分类号： H03M7/38

    CPC分类号： G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  H03K19/17736 ,  H03K19/1776

    摘要： An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

    摘要翻译： SRAM总线架构包括直通互连导体。 每个直通互连导体通过包括与三态缓冲器并联连接的传输晶体管的元件连接到FPGA的通用互连架构的路由通道。 传输晶体管和三态缓冲器由配置SRAM位控制。 一些直通互连导体通过可编程元件连接到SRAM块的地址，数据和控制信号线，而其他通过SRAM块进一步连接到SRAM总线架构。

    SRAM bus architecture and interconnect to an FPGA
    5.
    发明申请
    SRAM bus architecture and interconnect to an FPGA 失效

    公开(公告)号：US20060193181A1

    公开(公告)日：2006-08-31

    申请号：US11410415

    申请日：2006-04-24

    申请人： William Plants

    发明人： William Plants

    IPC分类号： G11C5/00 ,  G11C7/10

    CPC分类号： G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  H03K19/17736 ,  H03K19/1776

    摘要： An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

    Flash-based FPGA with secure reprogramming
    7.
    发明授权
    Flash-based FPGA with secure reprogramming 有权
    基于闪存的FPGA，具有安全的重新编程

    公开(公告)号：US07616508B1

    公开(公告)日：2009-11-10

    申请号：US11463846

    申请日：2006-08-10

    申请人： Joel Landry ,  William Plants ,  Randall Sexton

    发明人： Joel Landry ,  William Plants ,  Randall Sexton

    IPC分类号： G11C7/00 ,  G06F17/50

    CPC分类号： H03K19/17748 ,  G11C16/102 ,  H03K19/17732 ,  H03K19/17768

    摘要： A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.

    摘要翻译： 基于闪存的可编程集成电路包括可编程电路，耦合到可编程电路的闪存阵列，用于配置它，用于对闪速存储器阵列进行编程的闪存编程电路，以及诸如微控制器或状态机的片上智能，耦合 编程电路通过I / O焊盘提供的片外数据对闪速存储器进行编程，或刷新存储在闪速存储器中的数据，以防止其降级。

    Deglitching circuits for a radiation-hardened static random access memory based programmable architecture
    9.
    发明申请
    Deglitching circuits for a radiation-hardened static random access memory based programmable architecture 有权

    公开(公告)号：US20060126376A1

    公开(公告)日：2006-06-15

    申请号：US11323417

    申请日：2005-12-30

    申请人： William Plants

    发明人： William Plants

    IPC分类号： G11C11/41 ,  G11C11/00

    CPC分类号： G11C11/4125

    摘要： The present invention comprises a device and a method for a deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array. The deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array comprises a configuration memory that has a plurality of configuration bits Read and write circuitry is provided to configure the plurality of configuration bits. A radiation hard latch is coupled to and controls a programmable element and an interface couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the plurality of configuration bits.