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    Method of manufacturing semiconductor structures including a pair of MOSFETs
    1.
    发明授权
    Method of manufacturing semiconductor structures including a pair of MOSFETs 有权
    制造包括一对MOSFET的半导体结构的方法

    公开(公告)号：US6096664A

    公开(公告)日：2000-08-01

    申请号：US130324

    申请日：1998-08-06

    申请人： Thomas S. Rupp ,  Stephan Kudelka ,  Jeffrey Gambino ,  Mary Weybright

    发明人： Thomas S. Rupp ,  Stephan Kudelka ,  Jeffrey Gambino ,  Mary Weybright

    IPC分类号： H01L21/308 ,  H01L21/334 ,  H01L21/8234 ,  H01L27/088

    CPC分类号： H01L21/823462

    摘要： A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface of the silicon substrate. One portion of the silicon dioxide layer is over a first isolated region and another portion of the silicon dioxide layer being over a second isolated region. An inorganic layer is formed over the silicon dioxide layer extending over the isolated regions of the silicon substrate. A first portion of the inorganic layer is over the first isolated regions and a second portion of the inorganic layer is over the second isolated regions. A photoresist layer is formed over the inorganic layer. The photoresist layer is patterned with a window over the first portion of the inorganic layer. The photoresist layer covers the second portion of the inorganic layer. The inorganic layer is patterned into an inorganic mask by bringing a etch into contact with the patterned photoresist layer to selectively remove the first portion of the inorganic layer an thereby expose an underlying portion of the surface of the silicon substrate while leaving the second portion of the inorganic layer. The inorganic mask is used to selectively remove exposed portions of the grown silicon dioxide. The inorganic mask is removed. A second layer of silicon dioxide is grown over the exposed underlying portion of the silicon substrate to a thickness different from the thickness of the first layer of silicon dioxide. The silicon dioxide layers are patterned into gate oxides for each of a corresponding one of the pair of MOSFETs.

    摘要翻译： 一种用于在硅衬底的不同电隔离区域中形成一对MOSFET的方法。 每个MOSFET具有不同的栅极氧化物厚度。 在硅衬底的表面上生长第一层二氧化硅至预定厚度。 二氧化硅层的一部分在第一隔离区上方，二氧化硅层的另一部分在第二隔离区之上。 在硅衬底的隔离区域上延伸的二氧化硅层之上形成无机层。 无机层的第一部分在第一隔离区之上，无机层的第二部分在第二隔离区之上。 在无机层上形成光致抗蚀剂层。 在无机层的第一部分上的窗口对光致抗蚀剂层进行图案化。 光致抗蚀剂层覆盖无机层的第二部分。 通过使蚀刻与图案化的光致抗蚀剂层接触来将无机层图案化成无机掩模，以选择性地去除无机层的第一部分，从而暴露硅衬底的表面的下面部分，同时留下第二部分的 无机层。 无机掩模用于选择性地去除生长的二氧化硅的暴露部分。 去除无机掩模。 第二层二氧化硅在硅衬底的暴露下面的部分上生长到与第一层二氧化硅的厚度不同的厚度。 将二氧化硅层图案化成对于一对MOSFET中的每一个的栅极氧化物。

    Dual gate oxide process for uniform oxide thickness
    2.
    发明授权
    Dual gate oxide process for uniform oxide thickness 有权
    双栅氧化法，均匀氧化物厚度

    公开(公告)号：US06261972B1

    公开(公告)日：2001-07-17

    申请号：US09706641

    申请日：2000-11-06

    申请人： Helmut Horst Tews ,  Mary Weybright ,  Stephan Kudelka ,  Oleg Gluschenkov ,  Suri Hegde

    发明人： Helmut Horst Tews ,  Mary Weybright ,  Stephan Kudelka ,  Oleg Gluschenkov ,  Suri Hegde

    IPC分类号： H01L2100

    CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

    摘要： A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising: a) growing a sacrificial oxide layer on a substrate; b) implanting a dopant through the sacrificial oxide layer; c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface; e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide; f) implanting a second dosage of nitrogen ions through the photoresist; g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

    摘要翻译： 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以允许氮扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双栅氧化物的薄氧化物的位置; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

    Selective etching to increase trench surface area
    3.
    发明授权
    Selective etching to increase trench surface area 有权
    选择性蚀刻以增加沟槽表面积

    公开(公告)号：US07157328B2

    公开(公告)日：2007-01-02

    申请号：US11047312

    申请日：2005-01-31

    申请人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

    发明人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/30604 ,  H01L29/66181

    摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

    摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

    Selective etching to increase trench surface area
    4.
    发明申请
    Selective etching to increase trench surface area 有权
    选择性蚀刻以增加沟槽表面积

    公开(公告)号：US20060172486A1

    公开(公告)日：2006-08-03

    申请号：US11047312

    申请日：2005-01-31

    申请人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

    发明人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L21/30604 ,  H01L29/66181

    摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

    摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell
    7.
    发明申请
    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell 失效
    用于制造具有绝缘环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到衬底，特别是用于半导体存储器单元

    公开(公告)号：US20050026384A1

    公开(公告)日：2005-02-03

    申请号：US10901406

    申请日：2004-07-27

    申请人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sanger

    发明人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sanger

    IPC分类号： H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

    摘要： Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

    摘要翻译： 在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供 在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个 填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。

    High aspect ratio PBL SiN barrier formation
    8.
    发明授权
    High aspect ratio PBL SiN barrier formation 有权
    高纵横比PBL SiN阻挡层形成

    公开(公告)号：US06677197B2

    公开(公告)日：2004-01-13

    申请号：US10032040

    申请日：2001-12-31

    申请人： Stephan Kudelka ,  Helmut Horst Tews

    发明人： Stephan Kudelka ,  Helmut Horst Tews

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L29/66181

    摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.

    摘要翻译： 在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a） 在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模 衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物 在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物 进行多化学机械抛光。

    Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation
    10.
    发明授权
    Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation 失效
    用于单面垂直器件形成的自对准，亚光刻分辨率图案的负离子注入掩模形成

    公开(公告)号：US06498061B2

    公开(公告)日：2002-12-24

    申请号：US09730674

    申请日：2000-12-06

    申请人： Rama Divakaruni ,  Stephan Kudelka ,  Helmut Tews ,  Irene McStay ,  Kil-Ho Lee ,  Uwe Schroeder

    发明人： Rama Divakaruni ,  Stephan Kudelka ,  Helmut Tews ,  Irene McStay ,  Kil-Ho Lee ,  Uwe Schroeder

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867

    摘要： A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

    摘要翻译： 用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。 在沟槽填充材料上形成薄膜，氮化硅，阻挡层。 在阻挡层上沉积非晶硅掩模层的薄膜。 对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。 从深沟槽剥离非晶硅掩模层的未掺杂部分。 然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。 反映出暴露部分的沟槽填充材料。 氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。