公开(公告)号：US6096664A

公开(公告)日：2000-08-01

申请号：US130324

申请日：1998-08-06

申请人： Thomas S. Rupp ,  Stephan Kudelka ,  Jeffrey Gambino ,  Mary Weybright

发明人： Thomas S. Rupp ,  Stephan Kudelka ,  Jeffrey Gambino ,  Mary Weybright

IPC分类号： H01L21/308 ,  H01L21/334 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823462

摘要： A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface of the silicon substrate. One portion of the silicon dioxide layer is over a first isolated region and another portion of the silicon dioxide layer being over a second isolated region. An inorganic layer is formed over the silicon dioxide layer extending over the isolated regions of the silicon substrate. A first portion of the inorganic layer is over the first isolated regions and a second portion of the inorganic layer is over the second isolated regions. A photoresist layer is formed over the inorganic layer. The photoresist layer is patterned with a window over the first portion of the inorganic layer. The photoresist layer covers the second portion of the inorganic layer. The inorganic layer is patterned into an inorganic mask by bringing a etch into contact with the patterned photoresist layer to selectively remove the first portion of the inorganic layer an thereby expose an underlying portion of the surface of the silicon substrate while leaving the second portion of the inorganic layer. The inorganic mask is used to selectively remove exposed portions of the grown silicon dioxide. The inorganic mask is removed. A second layer of silicon dioxide is grown over the exposed underlying portion of the silicon substrate to a thickness different from the thickness of the first layer of silicon dioxide. The silicon dioxide layers are patterned into gate oxides for each of a corresponding one of the pair of MOSFETs.

摘要翻译： 一种用于在硅衬底的不同电隔离区域中形成一对MOSFET的方法。 每个MOSFET具有不同的栅极氧化物厚度。 在硅衬底的表面上生长第一层二氧化硅至预定厚度。 二氧化硅层的一部分在第一隔离区上方，二氧化硅层的另一部分在第二隔离区之上。 在硅衬底的隔离区域上延伸的二氧化硅层之上形成无机层。 无机层的第一部分在第一隔离区之上，无机层的第二部分在第二隔离区之上。 在无机层上形成光致抗蚀剂层。 在无机层的第一部分上的窗口对光致抗蚀剂层进行图案化。 光致抗蚀剂层覆盖无机层的第二部分。 通过使蚀刻与图案化的光致抗蚀剂层接触来将无机层图案化成无机掩模，以选择性地去除无机层的第一部分，从而暴露硅衬底的表面的下面部分，同时留下第二部分的 无机层。 无机掩模用于选择性地去除生长的二氧化硅的暴露部分。 去除无机掩模。 第二层二氧化硅在硅衬底的暴露下面的部分上生长到与第一层二氧化硅的厚度不同的厚度。 将二氧化硅层图案化成对于一对MOSFET中的每一个的栅极氧化物。

公开(公告)号：US06261972B1

公开(公告)日：2001-07-17

申请号：US09706641

申请日：2000-11-06

申请人： Helmut Horst Tews ,  Mary Weybright ,  Stephan Kudelka ,  Oleg Gluschenkov ,  Suri Hegde

发明人： Helmut Horst Tews ,  Mary Weybright ,  Stephan Kudelka ,  Oleg Gluschenkov ,  Suri Hegde

IPC分类号： H01L2100

CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

摘要： A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising: a) growing a sacrificial oxide layer on a substrate; b) implanting a dopant through the sacrificial oxide layer; c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface; e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide; f) implanting a second dosage of nitrogen ions through the photoresist; g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

摘要翻译： 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以允许氮扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双栅氧化物的薄氧化物的位置; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

公开(公告)号：US06180975B2

公开(公告)日：2001-01-30

申请号：US09183306

申请日：1998-10-30

申请人： Carl J. Radens ,  Mary Weybright

发明人： Carl J. Radens ,  Mary Weybright

IPC分类号： H01L27108

CPC分类号： H01L27/10861 ,  H01L27/10832

摘要： A memory cell structure which uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor is described. The buried strap connection between the trench capacitor and the bitline contact in regions where the deep trench pattern intersects the active area of the device. The upper section of the trench contains a single crystalline material to minimize the amount of leakage. The memory cell structure includes a field-effect switch having a gate terminal which induces the depletion region in the substrate and the top of the trench, the extent of the depletion region varying as a function of a voltage applied to the gate terminal; a storage device that includes an isolation collar and a capacitor, the depletion region overlapping the isolation collar when the field-effect switch is in an off-state, and the depletion region does not overlap the isolation collar when the field effect switch is in an on-state.

摘要翻译： 描述了一种存储单元结构，其使用场效应控制的多数载波耗尽掩埋带区域来控制对沟槽电容器的访问。 在深沟槽图案与器件的有效区域相交的区域中，沟槽电容器和位线接触之间的埋入带连接。 沟槽的上部包含单晶材料以最小化泄漏量。 存储单元结构包括具有栅极端子的场效应开关，栅极端子引起衬底中的耗尽区域和沟槽的顶部，耗尽区域的程度随施加到栅极端子的电压而变化; 包括隔离环和电容器的存储装置，当场效应开关处于断开状态时，耗尽区与隔离环重叠，当场效应开关处于断开状态时，耗尽区不与隔离环重叠 状态。

公开(公告)号：US20050037561A1

公开(公告)日：2005-02-17

申请号：US10604731

申请日：2003-08-13

申请人： Geng Wang ,  Kevin McStay ,  Mary Weybright ,  Yujun Li ,  Dureseti Chidambarrao

发明人： Geng Wang ,  Kevin McStay ,  Mary Weybright ,  Yujun Li ,  Dureseti Chidambarrao

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L21/26586 ,  H01L27/10864 ,  H01L29/1041 ,  H01L29/66537 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/945

摘要： A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ+δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source region

摘要翻译： 提供了形成深沟槽垂直晶体管的方法。 在掺杂半导体衬底中形成具有侧壁的深沟槽。 半导体衬底在其表面中包括反向漏极区域和沿着侧壁的通道。 漏极区域具有顶层和底层。 反向掺杂的源极区域形成在与通道下方的侧壁并置的衬底中。 栅极氧化层形成在与栅极导体并置的沟槽的侧壁上。 执行将栅极导体凹入低于漏极区域的底部电平的步骤，然后相对于反向掺杂物的垂直角进行成角度的离子注入进入源极区域下方的沟道，并以一定角度进行成角度的离子注入 相对于掺杂剂的垂直方向在源极区域下方的沟道中

公开(公告)号：US06656798B2

公开(公告)日：2003-12-02

申请号：US09965919

申请日：2001-09-28

申请人： Helmut Tews ,  Oleg Gluschenkov ,  Mary Weybright

发明人： Helmut Tews ,  Oleg Gluschenkov ,  Mary Weybright

IPC分类号： H01L21336

CPC分类号： H01L29/517 ,  H01L21/28238 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/42368

摘要： Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.

摘要翻译： 公开了一种在半导体晶片上处理半导体栅极结构的方法，该方法包括提供半导体结构，该半导体结构具有覆盖有由一个或多个隔离沟槽限定的焊盘氧化物层的有源器件区域，通过增厚所述焊盘来提供牺牲氧化物层 使用所述增厚衬垫氧化物层作为用于器件注入的牺牲氧化物层，在使用之后剥离所述牺牲衬垫氧化物层，并用最终栅极氧化物层封装所述半导体栅极。

公开(公告)号：US06670667B2

公开(公告)日：2003-12-30

申请号：US10213061

申请日：2002-08-06

申请人： Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

发明人： Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

IPC分类号： H01L27108

CPC分类号： H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4983

摘要： A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

公开(公告)号：US06458646B1

公开(公告)日：2002-10-01

申请号：US09608019

申请日：2000-06-30

申请人： Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

发明人： Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4983

摘要： A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

摘要翻译： 一种存储器件结构，包括其中形成有一个或多个非对称栅极的阵列器件区域，其中每个非对称栅极包括具有基本上垂直的侧壁的第一边缘和具有多晶硅台阶段的第二边缘，以及包括一个或多个 形成在其中的图案化栅极导体，其中支撑装置区域中的每个图案化栅极导体包括具有基本垂直侧壁的边缘。 该结构还可以包括位于阵列器件区域和支撑器件区域之间的电路器件区域，所述芯部器件区域包括一个或多个图案化栅极，每个栅极包括在栅极的每一侧上的多晶硅阶梯段。