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公开(公告)号：US20070243452A1
公开(公告)日：2007-10-18
申请号：US11734913
申请日：2007-04-13
申请人： Timothy W. Weidman , Karl J. Armstrong , David J. Eaglesham , Nety Krishna , Ralf Hofmann , Michael P. Stewart
发明人： Timothy W. Weidman , Karl J. Armstrong , David J. Eaglesham , Nety Krishna , Ralf Hofmann , Michael P. Stewart
CPC分类号： H01M4/8867 , C23C28/321 , C23C28/322 , C23C28/34 , C23C28/3455 , H01M4/8817 , H01M4/92 , H01M8/0206 , H01M8/021 , H01M8/023 , H01M8/0236 , H01M8/0245 , H01M8/086 , H01M8/1004 , Y02P70/56
摘要： The present invention generally relates to the creation of fuel cell components and the method of forming the various fuel cell components that have an improved lifetime, lower production cost and improved process performance. The invention generally includes treating or conditioning a substrate surface by depositing a material layer, or layers, having good adhesion to the substrate, low electrical resistivity (high conductivity) and has good resistance to chemical attack during the operation of fuel cell. The substrate may be, for example, a fuel cell part, a conductive plate, a separator plate, a bipolar plate or an end plate, among others. In one embodiment, the substrate surface is treated or conditioned by exposing at least a portion of it to a gas or liquid comprising ruthenium tetroxide.
摘要翻译： 本发明一般涉及燃料电池部件的制造和形成具有改善的寿命，降低生产成本和改进工艺性能的各种燃料电池部件的方法。 本发明通常包括通过沉积对基材具有良好粘附性的材料层或低层电阻（高导电性）并且在燃料电池操作期间具有良好的抗化学侵蚀性能来处理或调理基材表面。 基板可以是例如燃料电池部件，导电板，隔板，双极板或端板等。 在一个实施方案中，通过将其至少一部分暴露于包含四氧化钌的气体或液体来处理或调理基底表面。
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公开(公告)号：US08308858B2
公开(公告)日：2012-11-13
申请号：US12689176
申请日：2010-01-18
CPC分类号： C23C18/1893 , B82Y30/00 , C23C18/1651 , C23C18/32 , C23C18/34 , H01L21/02063 , H01L21/28518 , H01L21/288 , H01L21/76802 , H01L21/76814 , H01L21/76843 , H01L21/76847 , H01L21/76855 , H01L21/76856 , H01L21/76867 , H01L21/76874 , H01L21/76879 , H01L21/76889
摘要： Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.
摘要翻译： 本文所述的实施方案提供了在无电沉积工艺期间在基材上沉积材料的方法以及无电沉积溶液的组合物。 在一个实施例中，衬底包含具有暴露的硅接触表面的接触孔。 在另一个实施例中，衬底包含具有暴露的硅化物接触表面的接触孔。 通过将基板暴露于无电镀沉积工艺，用金属接触材料填充孔。 金属接触材料可以包含钴材料，镍材料或其合金。 在填充孔之前，衬底可以暴露于各种预处理工艺，例如预清洗工艺和激活工艺。 预清洗方法可以在湿式清洁工艺或等离子体蚀刻工艺期间去除有机残余物，天然氧化物和其它污染物。 该方法的实施方案还提供附加层的沉积，例如覆盖层。
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公开(公告)号：US20100107927A1
公开(公告)日：2010-05-06
申请号：US12689176
申请日：2010-01-18
IPC分类号： C23C18/50
CPC分类号： C23C18/1893 , B82Y30/00 , C23C18/1651 , C23C18/32 , C23C18/34 , H01L21/02063 , H01L21/28518 , H01L21/288 , H01L21/76802 , H01L21/76814 , H01L21/76843 , H01L21/76847 , H01L21/76855 , H01L21/76856 , H01L21/76867 , H01L21/76874 , H01L21/76879 , H01L21/76889
摘要： Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.
摘要翻译： 本文所述的实施方案提供了在无电沉积工艺期间在基材上沉积材料的方法以及无电沉积溶液的组合物。 在一个实施例中，衬底包含具有暴露的硅接触表面的接触孔。 在另一个实施例中，衬底包含具有暴露的硅化物接触表面的接触孔。 通过将基板暴露于无电镀沉积工艺，用金属接触材料填充孔。 金属接触材料可以包含钴材料，镍材料或其合金。 在填充孔之前，衬底可以暴露于各种预处理工艺，例如预清洗工艺和激活工艺。 预清洗方法可以在湿式清洁工艺或等离子体蚀刻工艺期间去除有机残余物，天然氧化物和其它污染物。 该方法的实施方案还提供附加层的沉积，例如覆盖层。
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公开(公告)号：US07659203B2
公开(公告)日：2010-02-09
申请号：US11385043
申请日：2006-03-20
IPC分类号： H01L21/44
CPC分类号： C23C18/1893 , B82Y30/00 , C23C18/1651 , C23C18/32 , C23C18/34 , H01L21/02063 , H01L21/28518 , H01L21/288 , H01L21/76802 , H01L21/76814 , H01L21/76843 , H01L21/76847 , H01L21/76855 , H01L21/76856 , H01L21/76867 , H01L21/76874 , H01L21/76879 , H01L21/76889
摘要： Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.
摘要翻译： 本文所述的实施方案提供了在无电沉积工艺期间在基材上沉积材料的方法以及无电沉积溶液的组合物。 在一个实施例中，衬底包含具有暴露的硅接触表面的接触孔。 在另一个实施例中，衬底包含具有暴露的硅化物接触表面的接触孔。 通过将基板暴露于无电镀沉积工艺，用金属接触材料填充孔。 金属接触材料可以包含钴材料，镍材料或其合金。 在填充孔之前，衬底可以暴露于各种预处理工艺，例如预清洗工艺和激活工艺。 预清洗方法可以在湿式清洁工艺或等离子体蚀刻工艺期间去除有机残余物，天然氧化物和其它污染物。 该方法的实施方案还提供附加层的沉积，例如覆盖层。
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公开(公告)号：US20090014052A1
公开(公告)日：2009-01-15
申请号：US12234524
申请日：2008-09-19
IPC分类号： H02N6/00
CPC分类号： H01L31/046 , H01L31/0465 , Y02E10/50
摘要： In a module of photovoltaic cells, a method of forming the module interconnects includes a single cutting process after the deposition of all active layers. This simplifies the overall process to a set of vacuum steps followed by a set of interconnect steps, and may significantly module quality and yield. According to another aspect, an interconnect forming method includes self-aligned deposition of an insulator. This simplifies the process because no alignment is required. According to another aspect, an interconnect forming method includes a scribing process that results in a much narrower interconnect which may significantly boost cell efficiency, and allow for narrower cell sizes. According to another aspect, an interconnect includes an insulator layer that greatly reduces shunt current through the active layer, which can greatly improve cell efficiency.
摘要翻译： 在光伏电池的模块中，形成模块互连的方法包括在沉积所有有源层之后的单个切割工艺。 这将整个过程简化为一组真空步骤，随后是一组互连步骤，并且可以显着地模块质量和产量。 根据另一方面，互连形成方法包括绝缘体的自对准沉积。 这简化了过程，因为不需要对齐。 根据另一方面，互连形成方法包括划线过程，其导致更窄的互连，其可以显着提高电池效率，并且允许更窄的电池尺寸。 根据另一方面，互连包括绝缘体层，其大大减少了通过有源层的分流电流，这可以大大提高电池效率。
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公开(公告)号：US20090007957A1
公开(公告)日：2009-01-08
申请号：US12234509
申请日：2008-09-19
CPC分类号： H01L31/046 , H01L31/0465 , Y02E10/50
摘要： In a module of photovoltaic cells, a method of forming the module interconnects includes a single cutting process after the deposition of all active layers. This simplifies the overall process to a set of vacuum steps followed by a set of interconnect steps, and may significantly module quality and yield. According to another aspect, an interconnect forming method includes self-aligned deposition of an insulator. This simplifies the process because no alignment is required. According to another aspect, an interconnect forming method includes a scribing process that results in a much narrower interconnect which may significantly boost cell efficiency, and allow for narrower cell sizes. According to another aspect, an interconnect includes an insulator layer that greatly reduces shunt current through the active layer, which can greatly improve cell efficiency.
摘要翻译： 在光伏电池的模块中，形成模块互连的方法包括在沉积所有有源层之后的单个切割工艺。 这将整个过程简化为一组真空步骤，随后是一组互连步骤，并且可以显着地模块质量和产量。 根据另一方面，互连形成方法包括绝缘体的自对准沉积。 这简化了过程，因为不需要对齐。 根据另一方面，互连形成方法包括划线过程，其导致更窄的互连，其可以显着提高电池效率，并且允许更窄的电池尺寸。 根据另一方面，互连包括绝缘体层，其大大减少了通过有源层的分流电流，这可以大大提高电池效率。
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7.发明授权公开(公告)号：US07674662B2
公开(公告)日：2010-03-09
申请号：US11458511
申请日：2006-07-19
申请人： Yan Ye , John M. White , David J. Eaglesham
发明人： Yan Ye , John M. White , David J. Eaglesham
IPC分类号： H01L21/84
CPC分类号： H01L29/7869
摘要： The present invention comprises a method of forming a zinc oxide based thin film transistor by blanket depositing the zinc oxide layer and the source-drain metal layer and then wet etching through the zinc oxide while etching through the source-drain electrode layer. Thereafter, the active channel is formed by dry etching the source-drain electrode layer without effectively etching the zinc oxide layer.
摘要翻译： 本发明包括通过将氧化锌层和源极 - 漏极金属层进行橡皮沉积形成氧化锌基薄膜晶体管，然后在通过源 - 漏电极层进行蚀刻时通过氧化锌进行湿蚀刻的方法。 此后，通过干蚀刻源漏电极层形成有源沟道，而无需有效地蚀刻氧化锌层。
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公开(公告)号：US5169798A
公开(公告)日：1992-12-08
申请号：US546128
申请日：1990-06-28
IPC分类号： H01L21/203 , H01L31/18
CPC分类号： H01L31/184 , H01L21/02381 , H01L21/02395 , H01L21/0245 , H01L21/02463 , H01L21/02532 , H01L21/02546 , H01L21/02573 , H01L21/02631 , H01L31/1804 , Y02E10/544 , Y02E10/547 , Y02P70/521
摘要： Disclosed is a method of making a semiconductor device that comprises MBE at substrate temperatures substantially lower than conventionally used temperatures. A significant aspect of the method is the ability to produce highly doped (e.g., 10.sup.19 cm.sup.-3) epitaxial single crystal Si layers. The deposition can be carried out such that substantially all (at least 90%) dopant atoms are electrically active at 20.degree. C. However, the method is not limited to Si MBE. Exemplarily, the method can be used to produce epitaxial single crystal GaAs having very short (e.g.,
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公开(公告)号：US20080023065A1
公开(公告)日：2008-01-31
申请号：US11492277
申请日：2006-07-25
IPC分类号： H01L31/00
CPC分类号： H01L31/0465 , Y02E10/50
摘要： The present invention relates to configuring and wiring together cells in TF PV modules. According to one aspect, cells are fabricated on one plane on a top surface of a substrate, with wiring patterned on a parallel plane, and vias formed to provide connections between the cell plane and wiring plane. In one embodiment, the wiring plane is on the back surface of the substrate and vias are formed through the substrate. In another embodiment, the wiring plane is on the top surface of the substrate underneath the cell plane and an insulating layer, with the vias formed through the insulating layer. In another embodiment, the cell plane formed on the top surface includes superstrate cells that are illuminated through a transparent substrate, with an insulator between the cell plane and an upper wiring plane. According to another aspect, the heavy bus bar connections in the wiring plane can carry large currents and do not block light impinging on the cells. According to further aspects, the wiring plane enables use of parallel cell connections that provide immunity to shading, as described above. Moreover, these connections can be wired in a variety of methods, allowing use of series-parallel arrangements so that, for example, local regions could be parallel connected while larger regions series connected.
摘要翻译： 本发明涉及将光伏组件中的电池配置和接线在一起。 根据一个方面，在衬底的顶表面上的一个平面上制造电池，其中布线在平行平面上图案化，并且形成通孔以提供电池平面和布线平面之间的连接。 在一个实施例中，布线平面位于基板的背面，并且穿过基板形成通孔。 在另一个实施例中，布线平面位于单元平面下方的基板的顶表面和绝缘层，通孔通过绝缘层形成。 在另一个实施例中，形成在顶表面上的单元平面包括通过透明基板照射的透明单元，在单元平面和上布线平面之间具有绝缘体。 根据另一方面，布线平面中的重型母线连接可以承载大电流并且不阻挡撞击电池的光。 根据另外的方面，如上所述，布线平面能够使用提供对阴影的免疫力的并行单元连接。 此外，这些连接可以以各种方式布线，允许使用串并联装置，使得例如局部区域可以并联连接，而较大区域串联连接。
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10.发明申请公开(公告)号：US20080020550A1
公开(公告)日：2008-01-24
申请号：US11458511
申请日：2006-07-19
申请人： Yan Ye , John M. White , David J. Eaglesham
发明人： Yan Ye , John M. White , David J. Eaglesham
IPC分类号： H01L21/20 , H01L21/425
CPC分类号： H01L29/7869
摘要： The present invention comprises a method of forming a zinc oxide based thin film transistor by blanket depositing the zinc oxide layer and the source-drain metal layer and then wet etching through the zinc oxide while etching through the source-drain electrode layer. Thereafter, the active channel is formed by dry etching the source-drain electrode layer without effectively etching the zinc oxide layer.
摘要翻译： 本发明包括通过将氧化锌层和源极 - 漏极金属层进行橡皮沉积形成氧化锌基薄膜晶体管，然后在通过源 - 漏电极层进行蚀刻时通过氧化锌进行湿蚀刻的方法。 此后，通过干蚀刻源漏电极层形成有源沟道，而无需有效地蚀刻氧化锌层。
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