Method to form thick relaxed SiGe layer with trench structure
    1.
    发明授权
    Method to form thick relaxed SiGe layer with trench structure 失效
    形成具有沟槽结构的厚松弛SiGe层的方法

    公开(公告)号:US07226504B2

    公开(公告)日:2007-06-05

    申请号:US10062336

    申请日:2002-01-31

    IPC分类号: C30B33/02

    摘要: A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.

    摘要翻译: 形成具有较高锗含量和较低穿透位错密度的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度,其中SiGe层的锗含量按原子比大于20%; 将H +离子以约1.10×16cm -2至0.0010±0.2cm的剂量注入SiGe层中, SUP>,在约20keV至45keV之间的能量; 用光致抗蚀剂图案化SiGe层; 等离子体蚀刻结构以形成关于区域的沟槽; 去除光致抗蚀剂; 以及对基板和SiGe层进行热退火,以在惰性气氛中在约650℃至950℃的温度下放置SiGe层约30秒至30分钟。

    Patterned silicon submicron tubes
    2.
    发明申请
    Patterned silicon submicron tubes 失效
    图案硅亚微米管

    公开(公告)号:US20080164577A1

    公开(公告)日:2008-07-10

    申请号:US11649634

    申请日:2007-01-04

    IPC分类号: H01L21/3065 H01L29/06

    摘要: An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.

    摘要翻译: 亚微米硅(Si)管的阵列具有用于构图亚微米Si管的方法。 该方法提供Si衬底,并形成覆盖Si衬底的二氧化硅膜。 由二氧化硅膜形成二氧化硅棒的阵列,并且在二氧化硅棒周围形成Si 3 N 4 N 4管。 二氧化硅棒被蚀刻掉。 然后,蚀刻Si衬底的暴露区域,形成Si 3 N 4 N 4管子下面的Si管。 最后,去除Si 3 N 4 N 4管。

    Patterned silicon submicron tubes
    3.
    发明授权
    Patterned silicon submicron tubes 失效
    图案硅亚微米管

    公开(公告)号:US07514282B2

    公开(公告)日:2009-04-07

    申请号:US11649634

    申请日:2007-01-04

    IPC分类号: H01L21/00

    摘要: An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.

    摘要翻译: 亚微米硅(Si)管的阵列具有用于构图亚微米Si管的方法。 该方法提供Si衬底,并形成覆盖Si衬底的二氧化硅膜。 由二氧化硅膜形成二氧化硅棒阵列,在二氧化硅棒周围形成Si 3 N 4管。 二氧化硅棒被蚀刻掉。 然后,蚀刻Si衬底的暴露区域,形成Si 3 N 4管下面的Si管。 最后,去除Si3N4管。

    Gallium nitride-on-silicon interface
    4.
    发明申请
    Gallium nitride-on-silicon interface 审中-公开
    氮化镓在硅界面

    公开(公告)号:US20080280426A1

    公开(公告)日:2008-11-13

    申请号:US11801210

    申请日:2007-05-09

    IPC分类号: H01L29/739 H01L21/20

    摘要: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.

    摘要翻译: 提供了一种在硅(Si)和氮化镓(GaN)膜之间形成匹配的热膨胀界面的方法。 该方法提供(111)Si衬底并且在压缩覆盖Si衬底上形成第一含铝(Al)的膜。 在第一含Al膜中形成纳米柱孔,其暴露下面的Si衬底的区域。 从暴露区域选择性地生长GaN层,覆盖第一含Al膜。 使用横向纳米外延生长(LNEO)工艺生长GaN。 重复上述过程,在压缩中形成第二含Al膜,在第二含Al膜中形成纳米柱孔,并选择性地生长第二GaN层。 可以最初在低温下生长诸如Al 2 O 3 3,Si 1-x Ge x,InP,GaP,GaAs,AlN,AlGaN或GaN的膜材料。 通过增加生长温度,可以在Si衬底上形成外延GaN的压缩层。

    Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers
    7.
    发明申请
    Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers 失效
    使用多个铝化合物缓冲层的氮化镓 - 硅 - 硅界面

    公开(公告)号:US20090008647A1

    公开(公告)日:2009-01-08

    申请号:US11825427

    申请日:2007-07-06

    IPC分类号: H01L29/15 H01L21/20

    摘要: A thermal expansion interface between silicon (Si) and gallium nitride (GaN) films using multiple buffer layers of aluminum compounds has been provided, along with an associated fabrication method. The method provides a (111) Si substrate and deposits a first layer of AlN overlying the substrate by heating the substrate to a relatively high temperature of 1000 to 1200° C. A second layer of AlN is deposited overlying the first layer of AlN at a lower temperature of 500 to 800° C. A third layer of AlN is deposited overlying the second layer of AlN by heating the substrate to the higher temperature range. Then, a grading Al1-XGaXN layer is formed overlying the third layer of AlN, where 0

    摘要翻译: 已经提供了使用多种铝化合物缓冲层的硅(Si)和氮化镓(GaN)膜之间的热膨胀界面,以及相关的制造方法。 该方法提供(111)Si衬底,并通过将衬底加热至1000至1200℃的较高温度,将衬底上的第一层AlN沉积在衬底上。在第一层AlN上沉积第二层AlN, 较低温度为500至800℃。通过将衬底加热到​​较高温度范围,沉积第三层AlN,覆盖第二层AlN。 然后,形成覆盖在第一层次Al1-XGaXN层上的固定组成Al1-XGaXN层的覆盖在第三层AlN上的分级Al1-XGaXN层,其中0

    Gallium nitride-on-silicon multilayered interface
    8.
    发明申请
    Gallium nitride-on-silicon multilayered interface 审中-公开
    氮化镓 - 硅多层界面

    公开(公告)号:US20080296625A1

    公开(公告)日:2008-12-04

    申请号:US11810022

    申请日:2007-06-04

    IPC分类号: H01L29/06 H01L21/20

    摘要: A multilayer thermal expansion interface between silicon (Si) and gallium nitride (GaN) films is provided, along with an associated fabrication method. The method provides a (111) Si substrate and forms a first layer of a first film overlying the substrate. The Si substrate is heated to a temperature in the range of about 300 to 800° C., and the first layer of a second film is formed in compression overlying the first layer of the first film. Using a lateral nanoheteroepitaxy overgrowth (LNEO) process, a first GaN layer is grown overlying the first layer of second film. Then, the above-mentioned processes are repeated: forming a second layer of first film; heating the substrate to a temperature in the range of about 300 to 800° C.; forming a second layer of second film in compression; and, growing a second GaN layer using the LNEO process.

    摘要翻译: 提供硅(Si)和氮化镓(GaN)膜之间的多层热膨胀界面以及相关的制造方法。 该方法提供(111)Si衬底并且形成覆盖衬底的第一膜的第一层。 将Si衬底加热至约300至800℃的温度,并且第二膜的第一层以压缩形式覆盖第一膜的第一层。 使用横向纳米外延过度生长(LNEO)工艺,生长第一GaN层,覆盖第一层第二层膜。 然后,重复上述过程:形成第二层第一膜; 将基板加热至约300至800℃的温度; 在压缩中形成第二层第二膜; 并且使用LNEO工艺生长第二GaN层。

    Silicon nanostructures and fabrication thereof
    10.
    发明申请
    Silicon nanostructures and fabrication thereof 审中-公开
    硅纳米结构及其制造

    公开(公告)号:US20080166878A1

    公开(公告)日:2008-07-10

    申请号:US11651242

    申请日:2007-01-08

    IPC分类号: H01L21/306

    摘要: A method of fabricating silicon nanostructures includes preparing a silicon wafer as a substrate; forming an oxide layer hardmask directly on the silicon substrate; patterning and etching the oxide hardmask; wet etching the silicon wafer to remove oxide to reduce the size of the oxide hardmask and to form nanostructure elements; and dry etching, in one or more steps, the silicon wafer using the oxide hardmask to form a desired nanostructure having substantially parallel vertical sidewalls thereon.

    摘要翻译: 制造硅纳米结构的方法包括制备硅晶片作为基底; 在硅衬底上直接形成氧化层硬掩模; 图案化和蚀刻氧化物硬掩模; 湿蚀刻硅晶片以除去氧化物以减小氧化物硬掩模的尺寸并形成纳米结构元件; 以及使用氧化物硬掩模在一个或多个步骤中干蚀刻硅晶片以形成其上具有基本上平行的垂直侧壁的所需纳米结构。