公开(公告)号：US20240203797A1

公开(公告)日：2024-06-20

申请号：US18081207

申请日：2022-12-14

Applicant: Tokyo Electron Limited

Inventor： Andrew WELOTH ,  Daniel FULFORD ,  Anthony SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton DEVILLIERS ,  David CONKLIN

IPC: H01L21/66 ,  G03F7/00 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L22/20 ,  G03F7/0035 ,  H01L21/02002 ,  H01L21/67092 ,  H01L21/67288

Abstract: Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.

公开(公告)号：US20220336226A1

公开(公告)日：2022-10-20

申请号：US17703072

申请日：2022-03-24

Applicant: Tokyo Electron Limited

Inventor： Charlotte CUTLER ,  Michael MURPHY ,  David CONKLIN

IPC: H01L21/324 ,  G03F7/00

Abstract: Techniques herein include methods for forming a direct write, tunable stress film and methods for correcting wafer bow using said stress film. The method can be executed on a coater-developer tool or track-based tool. The stress film can be based on a film that undergoes crosslinking/decrosslinking under external stimulus where direct write is achieved by, but is not limited to, 365 nm exposure and subsequent cure is used to “pattern-in” stress. No develop step may be required, which provides additional significant benefit in conserving film planarity. An amount of bow (or internal stress to create or affect a bow signature) can be tuned with exposure dose, bake temperature, bake time and number of bakes.

公开(公告)号：US20240203778A1

公开(公告)日：2024-06-20

申请号：US18085354

申请日：2022-12-20

Applicant: Tokyo Electron Limited

Inventor： David POWER ,  David CONKLIN ,  Anthony SCHEPIS ,  Andrew WELOTH ,  Anton DEVILLIERS

IPC: H01L21/68 ,  H01L21/67 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L21/681 ,  H01L21/67265 ,  H01L21/6835 ,  H01L23/544 ,  H01L2221/68363 ,  H01L2223/54426

Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.

公开(公告)号：US20230352343A1

公开(公告)日：2023-11-02

申请号：US18308230

申请日：2023-04-27

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  David POWER ,  Eric Chih-Fang LIU ,  Anton J. DEVILLIERS ,  Kandabara TAPILY ,  Jodi GRZESKOWIAK ,  David CONKLIN ,  Michael MURPHY

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L23/5226

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.