公开(公告)号：US20240222313A1

公开(公告)日：2024-07-04

申请号：US18089732

申请日：2022-12-28

Applicant: International Business Machines Corporation

Inventor： Roy R. Yu ,  Katsuyuki Sakuma

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/80 ,  H01L21/6838 ,  H01L21/78 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80019 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948

Abstract: An apparatus for bonding a first substrate to a second substrate includes a heatable mounting stage configured to accommodate a first semiconductor substrate on an upward-facing surface and a first stack of semiconductor materials on the first semiconductor substrate; a heatable bond head configured to accommodate a second semiconductor substrate on a downward-facing surface and a second stack of semiconductor materials on the second semiconductor substrate; and a collet disposed on the downward-facing surface of the heatable bond head and configured to receive the second semiconductor substrate and the second stack of semiconductor materials. The heatable bond head is configured to have a vacuum applied thereto to deformably accommodate the second semiconductor substrate and the second stack of semiconductor materials against the collet. The heatable bond head is configured to be pressed against the heatable mounting stage to bond the semiconductor materials.

公开(公告)号：US11978719B2

公开(公告)日：2024-05-07

申请号：US17941461

申请日：2022-09-09

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Siping Hu

IPC: H01L23/00 ,  H01L27/146

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L27/14634 ,  H01L27/1469 ,  H01L2224/0812 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/80894 ,  H01L2224/80896

Abstract: A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

公开(公告)号：US20240047257A1

公开(公告)日：2024-02-08

申请号：US18480745

申请日：2023-10-04

Applicant: Tokyo Electron Limited

Inventor： Yoshitaka Otsuka

IPC: H01L21/68 ,  H01L21/67 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/681 ,  H01L21/67092 ,  H01L21/67103 ,  H01L21/67259 ,  H01L21/6838 ,  H01L24/80 ,  H01L2224/80011 ,  H01L2224/8013 ,  H01L2224/80896

Abstract: A bonding system includes a first holder and a second holder arranged to be spaced apart from each other in a vertical direction; a position adjuster configured to move the first holder and the second holder relatively to perform a position adjustment in a horizontal direction between a first substrate held by the first holder and a second substrate held by the second holder; a pressing unit configured to press the first substrate and the second substrate against each other; a measuring unit configured to measure a position deviation between an alignment mark on the first substrate and an alignment mark on the second substrate, the first substrate and the second substrate being bonded by the pressing unit; and a position adjustment controller configured to control the position adjustment in the horizontal direction in a currently-performed bonding processing based on the position deviation generated in a previously-performed bonding processing.

公开(公告)号：US20240021573A1

公开(公告)日：2024-01-18

申请号：US18353019

申请日：2023-07-14

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Pawel Mrozek

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80896 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80895 ,  H01L2224/80011

Abstract: Reliable hybrid bonded apparatuses are provided. An example process cleans nanoparticles from at least the smooth oxide top layer of a surface to be hybrid bonded after the surface has already been activated for the hybrid bonding. Conventionally, such an operation is discouraged. However, the example cleaning processes described herein increase the electrical reliability of microelectronic devices. Extraneous metal nanoparticles can enable undesirable current and signal leakage from finely spaced traces, especially at higher voltages with ultra-fine trace pitches. In the example process, the extraneous nanoparticles may be both physically removed and/or dissolved without detriment to the activated bonding surface.

公开(公告)号：US11798913B2

公开(公告)日：2023-10-24

申请号：US17658902

申请日：2022-04-12

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Siping Hu

IPC: H01L23/00 ,  H01L27/146

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L27/1469 ,  H01L27/14634 ,  H01L2224/0812 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/80894 ,  H01L2224/80896

Abstract: A metal-dielectric bonding method includes providing a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes: a first semiconductor layer including a complementary metal-oxide-semiconductor device, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, the first metal layer having a metal bonding surface. The metal bonding surface is planarized and a plasma treatment is applied thereto. The second semiconductor structure includes a second semiconductor layer including a pixel wafer, and a second dielectric layer on the second semiconductor layer, the second dielectric layer having a dielectric bonding surface. The dielectric bonding surface is planarized and a plasma treatment is applied thereto. The first and second semiconductor structures are bonded together by bonding the metal bonding surface with the dielectric bonding surface.

公开(公告)号：US20230187398A1

公开(公告)日：2023-06-15

申请号：US18147375

申请日：2022-12-28

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Guilian GAO ,  Javier A. DELACRUZ ,  Shaowu HUANG ,  Liang WANG ,  Gaius Giliman FOUNTAIN, JR. ,  Rajesh KATKAR ,  Cyprian Emeka UZOH

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L24/74 ,  H01L24/80 ,  H01L24/89 ,  H01L2224/05557 ,  H01L2224/06131 ,  H01L2224/06177 ,  H01L2224/8013 ,  H01L2224/08147 ,  H01L2224/80007 ,  H01L2224/80011 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/3512

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

公开(公告)号：US20180277585A1

公开(公告)日：2018-09-27

申请号：US15992908

申请日：2018-05-30

Applicant: Sony Corporation

Inventor： Yoshihisa Kagawa ,  Kenichi Aoyagi ,  Yoshiya Hagimoto ,  Nobutoshi Fujii

IPC: H01L27/146 ,  H01L21/768 ,  H04N5/369 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L27/06 ,  H01L23/48

CPC classification number: H01L27/14636 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/83 ,  H01L27/0688 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/1469 ,  H01L2221/1031 ,  H01L2224/02245 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80035 ,  H01L2224/80091 ,  H01L2224/80097 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/83345 ,  H01L2924/00014 ,  H01L2924/053 ,  H01L2924/12043 ,  H01L2924/13091 ,  H04N5/369 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/049 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

公开(公告)号：US20180151436A1

公开(公告)日：2018-05-31

申请号：US15573699

申请日：2016-05-12

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Aurélie TAUZIN ,  Bruno IMBERT

IPC: H01L21/78 ,  H01L21/324 ,  H01L23/00

CPC classification number: H01L21/7806 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/76254 ,  H01L24/80 ,  H01L31/0725 ,  H01L31/0735 ,  H01L2224/80004 ,  H01L2224/80011 ,  H01L2224/80055 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80894 ,  H01L2224/80948 ,  H01L2924/10329 ,  H01L2924/10335

Abstract: The method is carried out of a first substrate having a first layer made of a first material with a second substrate having a second layer made of a second material, the first material and the second material being of different natures and selected from alloys of elements of columns III and V, the method having the steps of: a) providing the first substrate and the second substrate, b) bringing the first substrate into contact with the second substrate so as to form a bonding interface between the first layer and the second layer, c) performing a first heat treatment at a first predefined temperature, d) thinning one of the substrates, e) depositing, at a temperature less than or equal to the first predefined temperature, a barrier layer, on the thinned substrate, and f) performing a second heat treatment at a second predefined temperature, greater than the first predefined temperature.

公开(公告)号：US09842816B2

公开(公告)日：2017-12-12

申请号：US15228947

申请日：2016-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Chau Chen ,  Shih Pei Chou ,  Yen-Chang Chu ,  Cheng-Hsien Chou ,  Chih-Hui Huang ,  Yeur-Luen Tu

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L21/324 ,  H01L27/146 ,  H01L21/311 ,  H01L21/321 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/324 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03845 ,  H01L2224/039 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08057 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80121 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80906 ,  H01L2224/80948 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/04642

Abstract: A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

公开(公告)号：US09837287B2

公开(公告)日：2017-12-05

申请号：US15482346

申请日：2017-04-07

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Yuankun Hou ,  Kuanchieh Yu ,  Yu Hua ,  Yuelin Zhao

IPC: H01L21/30 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/10 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/56 ,  H01L21/30604 ,  H01L21/308 ,  H01L22/12 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05571 ,  H01L2224/0612 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29078 ,  H01L2224/30145 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/80011 ,  H01L2224/80203 ,  H01L2224/80805 ,  H01L2224/8081 ,  H01L2224/80895 ,  H01L2224/83011 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/8381 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/163 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/2919 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/80

Abstract: A method of forming a sealing structure for a bonded wafer is provided. The method includes providing the lower wafer and the upper wafer, forming a sealing material layer on each of the lower wafer and the upper wafer, forming a mask layer on the sealing material layer on each of the lower wafer and the upper wafer, etching the sealing material layer using the mask layer as an etch mask, so as to form a first protrusion at an edge of the lower wafer and a second protrusion at an edge of the upper wafer, and bonding the first protrusion and the second protrusion together to form the sealing structure. The sealing structure encloses a gap between the lower wafer and the upper wafer at an edge of the bonded wafer, so as to form a hermetically sealed cavity at the edge of the bonded wafer.