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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06777758B2

    公开(公告)日：2004-08-17

    申请号：US09754325

    申请日：2001-01-05

    申请人： Tomohiro Yamashita ,  Yoshinori Okumura ,  Katsuyuki Horita

    发明人： Tomohiro Yamashita ,  Yoshinori Okumura ,  Katsuyuki Horita

    IPC分类号： H01L2976

    CPC分类号： H01L21/28512 ,  H01L21/76895 ,  H01L21/823493

    摘要： P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50S) across the P wells (11, 12), so that the P wells (11, 12) are electrically connected with each other through the P-type layer (20). Contacts (31, 32) fill in contact holes (70H1, 70H2) formed in an interlayer isolation film (70) respectively in contact with the P-type layer (20). The contacts (31, 32) are connected to a wire (40). The wire (70) is connected to a prescribed potential, thereby fixing the P wells (11, 12) to prescribed potentials through the contacts (31, 32) and the P-type layer (20). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.

    摘要翻译： 具有不同杂质分布的P阱（11,12）相邻地形成在半导体衬底（50）的表面（50S）中。 在P阱（11,12）的表面（50S）中形成具有比P阱（11,12）低的电阻率的P型层（20），使得P阱（11,12）电 通过P型层（20）彼此连接。 接触件（31,32）分别填充形成在与P型层（20）接触的层间隔离膜（70）中的接触孔（70H1,70H2）。 触头（31,32）连接到导线（40）上。 电线（70）连接到规定电位，由此通过触点（31,32）和P型层（20）将P阱（11,12）固定到规定的电位。 因此，可以稳定地固定阱的电位，并且可以减少用于固定上述电位的元件的布局面积。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06399985B2

    公开(公告)日：2002-06-04

    申请号：US09750759

    申请日：2001-01-02

    申请人： Katsuyuki Horita ,  Takashi Kuroi ,  Yoshinori Okumura

    发明人： Katsuyuki Horita ,  Takashi Kuroi ,  Yoshinori Okumura

    IPC分类号： H01L2976

    CPC分类号： H01L21/823481 ,  H01L21/26586 ,  H01L21/76229 ,  H01L21/76235 ,  H01L27/0207 ,  H01L29/41758

    摘要： Provided are a semiconductor device that can obtain more output current without increasing the occupied area of a MOS transistor, and a method for manufacturing the same. MOS transistors (M11, M12) are electrically isolated by a trench isolation oxide film (21). The MOS transistor (M11) has a groove portion (GP) in which the width of the top is 20 nm to 80 nm and the depth is 50 nm to 150 nm. The groove portion (GP) is disposed at the boundary part between a trench isolation insulating film (22) and an active region (AR1) so as to surround the active region (AR1). A gate electrode (31A) is not only disposed above the active region (AR1) but also buried in the groove (GP) with a gate oxide film (30) interposed therebetween. Similarly, in the MOS transistor (M12), a groove portion (GP) is disposed at the boundary part between the trench isolation insulating film (21) and an active region (AR2) so as to surround the active region (AR2), and a gate electrode (32A) is also buried in the groove (GP) with the gate oxide film (30) interposed therebetween.

    摘要翻译： 提供一种可以在不增加MOS晶体管的占用面积的情况下获得更多的输出电流的半导体器件及其制造方法。 MOS晶体管（M11，M12）通过沟槽隔离氧化膜（21）电隔离。 MOS晶体管（M11）具有其顶部宽度为20nm〜80nm，深度为50nm〜150nm的槽部（GP）。 沟槽部分（GP）设置在沟道隔离绝缘膜（22）和有源区域（AR1）之间的边界部分，以围绕有源区域（AR1）。 栅电极（31A）不仅设置在有源区（AR1）的上方，而且还以栅介质膜（30）插入槽（GP）中。 类似地，在MOS晶体管（M12）中，沟槽部分（GP）设置在沟道隔离绝缘膜（21）和有源区域（AR2）之间的边界部分以包围有源区域（AR2），并且 栅极电极（32A）也被埋置在沟槽（GP）中，栅氧化膜（30）插入其间。

    Magnetic memory device
    6.
    发明授权
    Magnetic memory device 失效
    磁存储器件

    公开(公告)号：US07554837B2

    公开(公告)日：2009-06-30

    申请号：US12213505

    申请日：2008-06-20

    申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

    发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

    IPC分类号： G11C11/14 ,  G11C11/10

    CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

    摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

    摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

    Semiconductor device and method of manufacturing the same
    7.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06461920B1

    公开(公告)日：2002-10-08

    申请号：US09654877

    申请日：2000-09-05

    申请人： Masayoshi Shirahata ,  Yoshinori Okumura

    发明人： Masayoshi Shirahata ,  Yoshinori Okumura

    IPC分类号： H01L218236

    CPC分类号： H01L21/26513 ,  H01L21/74 ,  H01L27/088 ,  H01L29/105

    摘要： In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.

    摘要翻译： 在半导体器件中，在半导体衬底的主表面上形成具有不同阈值的相同导电类型的多个MIS晶体管，并且在深度方向上从半导体衬底的主表面延伸通过各个沟道区域 多个MIS晶体管的峰值位于不同深度处。 该结构通过在具有不同注入能量或不同离子种类的各个沟道区上进行的离子注入形成。 根据该半导体器件，可以单独地控制MIS晶体管的阈值，并且可以获得对于使用最佳的晶体管特性。

    Nonvolatile semiconductor memory device having a drain region of different impurity density and conductivity types
    8.
    发明授权
    Nonvolatile semiconductor memory device having a drain region of different impurity density and conductivity types 失效
    具有不同杂质密度和导电类型的漏区的非易失性半导体存储器件

    公开(公告)号：US06300656B1

    公开(公告)日：2001-10-09

    申请号：US08647532

    申请日：1996-05-15

    申请人： Shuichi Ueno ,  Shigeru Kusunoki ,  Yoshinori Okumura

    发明人： Shuichi Ueno ,  Shigeru Kusunoki ,  Yoshinori Okumura

    IPC分类号： G11C1134

    CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/66659 ,  H01L29/7835

    摘要： A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

    摘要翻译： 非易失性半导体存储器件包括在p型硅衬底的表面上与n +漏极扩散区域接触并覆盖其周围的n型区域。 该器件还包括与n型区域接触并覆盖其周边的p型​​杂质区域。 n +漏极扩散区域，n型区域和p +杂质区域延伸到位于浮置栅电极正下方的区域。 由此，非易失性半导体存储器件具有能够沿着栅电极方向注入高能电子的结构。

    MOS field effect transistor having source/drain regions surrounded by impurity wells
    9.
    发明授权
    MOS field effect transistor having source/drain regions surrounded by impurity wells 失效
    MOS场效应晶体管具有由杂质阱包围的源极/漏极区域

    公开(公告)号：US5536957A

    公开(公告)日：1996-07-16

    申请号：US637431

    申请日：1991-01-04

    申请人： Yoshinori Okumura

    发明人： Yoshinori Okumura

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/66575 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7836

    摘要： Disclosed is a MOSFET for controlling the flow of a large number of carriers from one source/drain region to the other source/drain region by applying a voltage to a gate. This MOSFET includes a semiconductor substrate and a transistor. The transistor includes a gate provided on the semiconductor substrate, one source/drain region and the other source/drain region both having a first conductivity type. The MOSFET includes first and second wells of a second conductivity type formed apart from each other on opposite sides of the gate in the main surface of the semiconductor substrate. The first well is such a small well as to accommodate only one source/drain region, while the second well is such a small well as to accommodate only the other source/drain region. The one source/drain region and the other source region are formed in the first and second wells, respectively. No distortion due to thermal stresses remains in the resultant MOSFET, and consequently a highly reliable MOSFET is obtained.

    摘要翻译： 公开了一种用于通过向栅极施加电压来控制大量载流子从一个源极/漏极区域到另一个源极/漏极区域的流动的MOSFET。 该MOSFET包括半导体衬底和晶体管。 晶体管包括设置在半导体衬底上的栅极，一个源极/漏极区域和另一个具有第一导电类型的源极/漏极区域。 MOSFET包括在半导体衬底的主表面中的栅极的相对侧上彼此分开形成的第二导电类型的第一阱和第二阱。 第一个阱是这样一个很小的井，只能容纳一个源极/漏极区，而第二个阱是这样一个很小的阱，只能容纳另一个源极/漏极区。 一个源极/漏极区域和另一个源极区域分别形成在第一和第二阱中。 所得到的MOSFET不会产生由于热应力引起的失真，因此获得高可靠性的MOSFET。

    Composite wiring layer
    10.
    发明授权
    Composite wiring layer 失效
    复合布线层

    公开(公告)号：US5502324A

    公开(公告)日：1996-03-26

    申请号：US363548

    申请日：1994-12-23

    申请人： Atsushi Hachisuka ,  Yoshinori Okumura

    发明人： Atsushi Hachisuka ,  Yoshinori Okumura

    IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/532 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  H01L29/43 ,  H01L29/49 ,  H01L29/417 ,  H01L29/423

    CPC分类号： H01L21/76897 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53271 ,  H01L27/10873 ,  H01L29/4983 ,  H01L2924/0002

    摘要： An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions formed as refractory metal silicide layers on opposite lateral walls of the first conductive portion. Upper surfaces and lateral surfaces thereof are coated with insulating layers formed in separate processes. The insulating layers covering the lateral surfaces in particular are formed by a self-aligning technique requiring no mask process. Where conductive layers are formed over the wiring layer according to this invention, a film forming and patterning process for insulating the conductive portions of the wiring layer is omitted and insulation of the wiring layer is secured.

    摘要翻译： 根据本发明的半导体器件的电极布线层包括由多晶硅等形成的第一导电部分和在第一导电部分的相对侧壁上形成为难熔金属硅化物层的第二导电部分。 其上表面和侧表面涂覆有分离工艺形成的绝缘层。 覆盖侧表面的绝缘层特别地由不需要掩模处理的自对准技术形成。 在根据本发明的布线层上形成导电层的情况下，省略了用于绝缘布线层的导电部分的成膜和图案化工艺，并且确保了布线层的绝缘。