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    Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
    1.
    发明授权
    Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer 失效
    形成包括半导体层和邻近半导体层内的开口的另一层的电子器件的工艺

    公开(公告)号：US07670895B2

    公开(公告)日：2010-03-02

    申请号：US11409633

    申请日：2006-04-24

    申请人： Toni D. Van Gompel ,  Peter J. Beckage ,  Mohamad M. Jahanbani ,  Michael D. Turner

    发明人： Toni D. Van Gompel ,  Peter J. Beckage ,  Mohamad M. Jahanbani ,  Michael D. Turner

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L21/823481 ,  H01L27/1203 ,  H01L29/78

    摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.

    摘要翻译： 形成电子器件的工艺可以包括图案化半导体层以限定开口。 在图案化半导体层之后，开口可以具有底部，并且半导体层可以具有侧壁和表面。 表面与开口的底部间隔开。 侧壁可以从开口的表面向底部延伸。 该工艺还可以包括在半导体层之上和在开口内形成层，以及从开口内去除第一层的一部分。 在去除层的一部分之后，层的剩余部分可以位于开口内并且邻近底部和侧壁，并且层的剩余部分可以与表面间隔开。 在另一方面，电子设备可以包括包括第一层的场隔离区域。

    Process of forming an electronic device including a layer formed using an inductively coupled plasma
    2.
    发明授权
    Process of forming an electronic device including a layer formed using an inductively coupled plasma 有权
    形成电子器件的工艺包括使用电感耦合等离子体形成的层

    公开(公告)号：US07491622B2

    公开(公告)日：2009-02-17

    申请号：US11409790

    申请日：2006-04-24

    申请人： Michael D. Turner ,  Mohamad M. Jahanbani ,  Toni D. Van Gompel ,  Mark D. Hall

    发明人： Michael D. Turner ,  Mohamad M. Jahanbani ,  Toni D. Van Gompel ,  Mark D. Hall

    IPC分类号： H01L21/76 ,  H01L23/58

    CPC分类号： H01L21/02274 ,  H01L21/02211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/3185 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84

    摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include chemical vapor depositing a first layer adjacent to the sidewall, wherein the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. Chemical vapor depositing the first layer can be performed using an inductively coupled plasma.

    摘要翻译： 形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。 在图案化半导体层之后，半导体层可以具有侧壁和表面，表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。 该方法还可以包括化学气相沉积邻近侧壁的第一层，其中第一层位于开口内且与侧壁相邻并且与表面间隔开。 可以使用电感耦合等离子体进行沉积第一层的化学气相沉积。

    Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer
    3.
    发明授权
    Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer 有权
    形成电子器件的工艺包括与半导体层内的开口相邻的致密的氮化物层

    公开(公告)号：US07528078B2

    公开(公告)日：2009-05-05

    申请号：US11433298

    申请日：2006-05-12

    申请人： Toni D. Van Gompel ,  Kuang-Hsin Chen ,  Laegu Kang ,  Rode R. Mora ,  Michael D. Turner

    发明人： Toni D. Van Gompel ,  Kuang-Hsin Chen ,  Laegu Kang ,  Rode R. Mora ,  Michael D. Turner

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/31111 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76205

    摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.

    摘要翻译： 形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。 在图案化半导体层之后，开口可以具有底部，并且半导体层可以具有侧壁和表面。 表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。 该方法还可以包括在开口内沉积氮化物层，其中使用PECVD技术进行沉积。 该方法还可以包括使氮化物层致密化。 该方法还可以进一步包括去除氮化物层的一部分，其中氮化物层的剩余部分可以位于开口内并且与表面间隔开。

    Method for elimination of excessive field oxide recess for thin Si SOI
    8.
    发明授权
    Method for elimination of excessive field oxide recess for thin Si SOI 有权
    消除薄Si SOI的过量场氧化物凹陷的方法

    公开(公告)号：US07037857B2

    公开(公告)日：2006-05-02

    申请号：US10737115

    申请日：2003-12-16

    申请人： Toni D. Van Gompel ,  Mark D. Hall ,  Mohamad Jahanbani ,  Michael D. Turner

    发明人： Toni D. Van Gompel ,  Mark D. Hall ,  Mohamad Jahanbani ,  Michael D. Turner

    IPC分类号： H01L21/3205 ,  H01L21/31

    CPC分类号： H01L21/76283

    摘要： A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than 50 Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.

    摘要翻译： 在SOI衬底中形成沟槽隔离的方法开始于衬底氧化物，然后在SOI衬底的上半导体层上方具有抗反射涂层（ARC）。 衬垫氧化物保持不大于约100埃的厚度。 形成用于沟槽隔离的开口，其延伸到上半导体层下方的氧化物中以暴露其表面。 衬垫氧化物沿其侧壁凹陷，具有各向同性蚀刻。 其后是沿着开口的侧壁生长的薄的，不大于50埃的氧化物。 这种生长的氧化物避免在ARC和衬垫氧化物之间形成凹陷，并且还避免在低氧化物层的表面和生长的氧化物之间形成空隙。 这导致当形成随后的多晶硅栅极层时避免多晶硅桁条。

    Isolation trench
    9.
    发明授权
    Isolation trench 有权
    隔离槽

    公开(公告)号：US06979627B2

    公开(公告)日：2005-12-27

    申请号：US10836150

    申请日：2004-04-30

    申请人： Choh-Fei Yeap ,  Yongjoo Jeon ,  Michael D. Turner ,  Toni D. Van Gompel

    发明人： Choh-Fei Yeap ,  Yongjoo Jeon ,  Michael D. Turner ,  Toni D. Van Gompel

    IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/76283 ,  H01L21/84

    摘要： A process for forming an isolation trench in a wafer. The process includes depositing (e.g. by a directional deposition process) a first dielectric material in the trench and then depositing a second dielectric material (e.g. by a directional deposition process) over the first dielectric material in the trench. A third material is deposited in the trench on the second layer. The second material and the third material are selectively etchable with respect to each other. In one example, the first material has a lower dielectric constant than the second material.

    摘要翻译： 一种用于在晶片中形成隔离沟槽的工艺。 该方法包括在沟槽中沉积（例如通过定向沉积工艺）第一介电材料，然后在沟槽中的第一介电材料上沉积第二电介质材料（例如通过定向沉积工艺）。 第三材料沉积在第二层上的沟槽中。 第二材料和第三材料相对于彼此可选择性地蚀刻。 在一个示例中，第一材料具有比第二材料低的介电常数。

    Method of forming a semiconductor isolation trench
    10.
    发明授权
    Method of forming a semiconductor isolation trench 有权
    形成半导体隔离沟槽的方法

    公开(公告)号：US07687370B2

    公开(公告)日：2010-03-30

    申请号：US11342102

    申请日：2006-01-27

    申请人： Toni D. Van Gompel ,  John J. Hackenberg ,  Rode R. Mora ,  Suresh Venkatesan

    发明人： Toni D. Van Gompel ,  John J. Hackenberg ,  Rode R. Mora ,  Suresh Venkatesan

    IPC分类号： H01L21/76 ,  H01L21/311 ,  H01L21/302

    CPC分类号： H01L21/76224 ,  Y10S438/911

    摘要： A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a part of the barrier layer and at least a part of the pad oxide layer are etched through the at least one opening resulting in a trench pad oxide layer. Etching of the trench pad oxide layer stops substantially at a top surface of the substrate within the isolation trench. An oxide layer is grown by diffusion on at least the top surface of the substrate corresponding to the at least one isolation trench. The method further includes etching the oxide layer and at least a portion of the substrate to form at least one isolation trench opening.

    摘要翻译： 用于形成半导体隔离沟槽的方法包括在衬底上形成衬垫氧化物层，并在衬底上形成阻挡层。 掩模层形成在阻挡层之上，并被图案化以在掩模层中形成至少一个开口。 阻挡层的至少一部分和衬垫氧化物层的至少一部分被蚀刻穿过至少一个开口，导致沟槽衬垫氧化物层。 沟槽衬垫氧化物层的蚀刻基本上在隔离沟槽内的衬底顶表面上停止。 氧化物层通过扩散至少对应于至少一个隔离沟槽的衬底的顶表面生长。 所述方法还包括蚀刻所述氧化物层和所述衬底的至少一部分以形成至少一个隔离沟槽开口。