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    Method of forming an interlayer dielectric
    1.
    发明申请
    Method of forming an interlayer dielectric 有权
    形成层间电介质的方法

    公开(公告)号：US20060281240A1

    公开(公告)日：2006-12-14

    申请号：US11148455

    申请日：2005-06-09

    申请人： Paul Grudowski ,  Stanley Filipiak ,  Yongjoo Jeon ,  Chad Weintraub

    发明人： Paul Grudowski ,  Stanley Filipiak ,  Yongjoo Jeon ,  Chad Weintraub

    IPC分类号： H01L21/469

    CPC分类号： H01L21/76834 ,  H01L21/31111

    摘要： A method for forming a semiconductor device comprises providing a semiconductor substrate; forming a first stressor layer over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer; forming a second stressor layer over the surface of the semiconductor substrate and the first stressor layer; and selectively removing portions of the second stressor layer using an isotropic etch. In one embodiment, the isotropic etch is a wet etch that selectively removes the second stressor layer without removing a significant amount of the first stressor layer and also planarizing a boundary between the first stressor layer and the second stressor layer.

    摘要翻译： 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底的表面上形成第一应力层; 选择性地去除所述第一应激层的部分; 在所述半导体衬底和所述第一应力层的表面上形成第二应力层; 并且使用各向同性蚀刻选择性地去除第二应力层的部分。 在一个实施例中，各向同性蚀刻是湿蚀刻，其在不去除大量的第一应力层的情况下选择性地去除第二应力层，并且还平面化第一应力层和第二应力层之间的边界。

    Method for forming multiple gate oxide thickness utilizing ashing and cleaning
    4.
    发明授权
    Method for forming multiple gate oxide thickness utilizing ashing and cleaning 失效
    使用灰化和清洁形成多个栅极氧化物厚度的方法

    公开(公告)号：US07041562B2

    公开(公告)日：2006-05-09

    申请号：US10696079

    申请日：2003-10-29

    申请人： Sangwoo Lim ,  Yongjoo Jeon ,  Choh-Fei Yeap

    发明人： Sangwoo Lim ,  Yongjoo Jeon ,  Choh-Fei Yeap

    IPC分类号： H01L21/311

    CPC分类号： H01L21/02054 ,  H01L21/823462 ,  H01L21/823857 ,  Y10S438/981

    摘要： Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric and the semiconductor substrate is protected to result in an improved (e.g. less rough) interface. One embodiment includes forming a dielectric layer overlying a substrate, partially etching the dielectric layer in at least one of the multiple regions, and ashing the dielectric layer. The remaining portion of the dielectric layer (due to the partial etch) may then help protect the underlying substrate from damage during a subsequent preclean. Afterwards, in one embodiment, the gate dielectric layer is grown to achieve a target gate dielectric thickness in at least one of the regions. This may also help further densify the gate dielectric layer. Processing may then be continued to form semiconductor devices in each of the multiple regions.

    摘要翻译： 本发明的实施例涉及具有多个栅介质结构的半导体结构。 一个实施例在具有不同介电厚度的多个区域中形成半导体器件，其中栅极电介质和半导体衬底之间的界面被保护以导致改进的（例如较不粗糙的）界面。 一个实施例包括形成覆盖衬底的电介质层，部分地蚀刻多个区域中的至少一个中的电介质层，以及灰化介电层。 电介质层的剩余部分（由于局部蚀刻）可能有助于保护下一层衬底在随后的预清洗过程中不被损坏。 之后，在一个实施例中，生长栅介质层以在至少一个区域中实现目标栅介质厚度。 这还可以有助于进一步增强栅极介质层的密度。 然后可以继续处理以在多个区域的每一个中形成半导体器件。

    Multiple gate dielectric structure and method for forming
    6.
    发明申请
    Multiple gate dielectric structure and method for forming 失效
    多栅电介质结构及其形成方法

    公开(公告)号：US20050093063A1

    公开(公告)日：2005-05-05

    申请号：US10696079

    申请日：2003-10-29

    申请人： Sangwoo Lim ,  Yongjoo Jeon ,  Choh-Fei Yeap

    发明人： Sangwoo Lim ,  Yongjoo Jeon ,  Choh-Fei Yeap

    IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/01 ,  H01L21/31 ,  H01L21/469 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L21/02054 ,  H01L21/823462 ,  H01L21/823857 ,  Y10S438/981

    摘要： Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric and the semiconductor substrate is protected to result in an improved (e.g. less rough) interface. One embodiment includes forming a dielectric layer overlying a substrate, partially etching the dielectric layer in at least one of the multiple regions, and ashing the dielectric layer. The remaining portion of the dielectric layer (due to the partial etch) may then help protect the underlying substrate from damage during a subsequent preclean. Afterwards, in one embodiment, the gate dielectric layer is grown to achieve a target gate dielectric thickness in at least one of the regions. This may also help further densify the gate dielectric layer. Processing may then be continued to form semiconductor devices in each of the multiple regions.

    摘要翻译： 本发明的实施例涉及具有多个栅介质结构的半导体结构。 一个实施例在具有不同介电厚度的多个区域中形成半导体器件，其中栅极电介质和半导体衬底之间的界面被保护以导致改进的（例如较不粗糙的）界面。 一个实施例包括形成覆盖衬底的电介质层，部分地蚀刻多个区域中的至少一个中的电介质层，以及灰化介电层。 电介质层的剩余部分（由于局部蚀刻）可能有助于保护下一层衬底在随后的预清洗过程中不被损坏。 之后，在一个实施例中，生长栅介质层以在至少一个区域中实现目标栅介质厚度。 这还可以有助于进一步增强栅极介质层的密度。 然后可以继续处理以在多个区域的每一个中形成半导体器件。

    Plasma enhanced nitride layer
    7.
    发明授权
    Plasma enhanced nitride layer 有权
    等离子体增强氮化物层

    公开(公告)号：US07074713B2

    公开(公告)日：2006-07-11

    申请号：US10954400

    申请日：2004-09-30

    申请人： Jian Chen ,  Stanley M. Filipiak ,  Yongjoo Jeon ,  Tab A. Stephens

    发明人： Jian Chen ,  Stanley M. Filipiak ,  Yongjoo Jeon ,  Tab A. Stephens

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76832 ,  H01L21/743 ,  H01L21/76834 ,  H01L21/76897

    摘要： An etch stop layer located over a plasma enhanced nitride (PEN) layer. Interlayer dielectric material is then formed over the etched stop layer. The etch stop layer is used as an etch stop for etching openings in the interlayer dielectric. In some embodiments, integrated circuits built with the PEN layer may include transistors with improved drive current at a given leakage current. Also, integrated circuits with the PEN layer may exhibit reduced parasitic capacitance.

    摘要翻译： 位于等离子体增强氮化物（PEN）层上方的蚀刻停止层。 然后在蚀刻的停止层上形成层间电介质材料。 蚀刻停止层用作用于蚀刻层间电介质中的开口的蚀刻停止层。 在一些实施例中，用PEN层构建的集成电路可以包括在给定泄漏电流下具有改善的驱动电流的晶体管。 此外，具有PEN层的集成电路可以表现出降低的寄生电容。

    Isolation trench
    8.
    发明授权
    Isolation trench 有权
    隔离槽

    公开(公告)号：US06979627B2

    公开(公告)日：2005-12-27

    申请号：US10836150

    申请日：2004-04-30

    申请人： Choh-Fei Yeap ,  Yongjoo Jeon ,  Michael D. Turner ,  Toni D. Van Gompel

    发明人： Choh-Fei Yeap ,  Yongjoo Jeon ,  Michael D. Turner ,  Toni D. Van Gompel

    IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/76283 ,  H01L21/84

    摘要： A process for forming an isolation trench in a wafer. The process includes depositing (e.g. by a directional deposition process) a first dielectric material in the trench and then depositing a second dielectric material (e.g. by a directional deposition process) over the first dielectric material in the trench. A third material is deposited in the trench on the second layer. The second material and the third material are selectively etchable with respect to each other. In one example, the first material has a lower dielectric constant than the second material.

    摘要翻译： 一种用于在晶片中形成隔离沟槽的工艺。 该方法包括在沟槽中沉积（例如通过定向沉积工艺）第一介电材料，然后在沟槽中的第一介电材料上沉积第二电介质材料（例如通过定向沉积工艺）。 第三材料沉积在第二层上的沟槽中。 第二材料和第三材料相对于彼此可选择性地蚀刻。 在一个示例中，第一材料具有比第二材料低的介电常数。

    Integrated circuit device and method therefor
    10.
    发明授权
    Integrated circuit device and method therefor 有权
    集成电路装置及其方法

    公开(公告)号：US06753242B2

    公开(公告)日：2004-06-22

    申请号：US10101298

    申请日：2002-03-19

    申请人： Geoffrey C-F Yeap ,  Srinivas Jallepalli ,  Yongjoo Jeon

    发明人： Geoffrey C-F Yeap ,  Srinivas Jallepalli ,  Yongjoo Jeon

    IPC分类号： H01L2131

    CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L21/31116 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66825

    摘要： A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

    摘要翻译： 在去除抗反射涂层（ARC）期间，半导体器件具有在基板中形成的凹陷，因为在蚀刻ARC期间这些凹陷位置被暴露。 虽然蚀刻剂被选择为在ARC材料和衬底材料之间的选择性，但是这种选择性受到限制，使得发生凹陷。 与这些凹陷的形成相关的问题是源极/漏极进一步扩散以与栅极重叠。 结果是晶体管可能具有减小的电流驱动。 通过等待执行ARC去除，至少在门周围形成侧壁间隔物之后，可以避免这个问题。 因此，随后的凹陷形成从栅极进一步发生，这导致减少或消除该凹陷可能导致希望延伸到栅极重叠的源/漏扩散的障碍。