公开(公告)号：US08647466B2

公开(公告)日：2014-02-11

申请号：US13095443

申请日：2011-04-27

Applicant: Tony Chiang

Inventor： Tony Chiang

IPC: H01L21/306

CPC classification number: H01L22/20

Abstract: Combinatorial evaluation of dry semiconductor processes is described, including rotating a mask comprising a plurality of apertures, wherein the mask is positioned between a dry semiconductor processing source and the substrate, and performing a dry semiconductor process through the apertures of the mask at a plurality of intervals during the rotating the mask to combinatorially create a plurality of processed regions on the substrate, wherein the apertures of the mask are arranged in such a way that the plurality of processed regions have different geometries relative to the processing source, and analyzing the processed regions to determine effects of time and geometry on the processed regions.

Abstract translation: 描述了干式半导体工艺的组合评估，包括旋转包括多个孔的掩模，其中掩模位于干燥半导体处理源和衬底之间，并且通过多个掩模的掩模的孔径执行干燥半导体工艺 在旋转掩模期间的间隔以组合地在基底上产生多个经处理的区域，其中掩模的孔以这样的方式排列，使得多个经处理的区域相对于处理源具有不同的几何形状，并且分析处理区域 以确定时间和几何对处理区域的影响。

公开(公告)号：US08609475B2

公开(公告)日：2013-12-17

申请号：US13602637

申请日：2012-09-04

Applicant: Zhi-Wen Sun ,  Tony Chiang ,  Chi-I Lang ,  Jinhong Tong

Inventor： Zhi-Wen Sun ,  Tony Chiang ,  Chi-I Lang ,  Jinhong Tong

IPC: H01L21/20 ,  H01L21/00 ,  H01L21/16 ,  H01L21/8229

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

Abstract: Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)2 film on the substrate, where the forming the Ni(OH)2 occurs at the cathode; and annealing the Ni(OH)2 film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)2 film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material.

Abstract translation: 在电阻式切换存储装置使用的基板上形成NiO膜的方法包括：制备镍离子溶液; 接收衬底，其中衬底包括底部电极，用作阴极的底部电极; 在衬底上形成Ni（OH）2膜，其中在阴极处形成Ni（OH）2; 并且还原Ni（OH）2膜以形成NiO膜，其中NiO膜形成电阻式开关存储元件的一部分。 在一些实施例中，方法还包括在NiO膜上形成顶部电极，并且在形成Ni（OH）2膜之前，预处理衬底。 在一些实施例中，呈现了底部电极和顶部电极为导电材料的方法。

公开(公告)号：US20130280853A1

公开(公告)日：2013-10-24

申请号：US13696635

申请日：2011-05-03

Applicant: Upendra Avachat ,  Tony Chiang ,  Craig Hunter ,  Jian Li ,  Guizhen Zhang

Inventor： Upendra Avachat ,  Tony Chiang ,  Craig Hunter ,  Jian Li ,  Guizhen Zhang

IPC: H01L31/05

CPC classification number: H01L31/0516 ,  C23C14/0623 ,  C23C14/165 ,  C23C14/3464 ,  C23C14/5866 ,  H01L21/02568 ,  H01L21/02614 ,  H01L21/02631 ,  H01L27/142 ,  H01L31/0322 ,  H01L31/0326 ,  H01L31/046 ,  Y02E10/541 ,  Y02P70/521

Abstract: The present disclosure is directed to methods of forming different types of Cu2ZnSnS4 (CZTS) solar cells and Copper Indium Gallium DiSelenide (CIGS) solar cells that can be combinatorially varied and evaluated. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.

Abstract translation: 本公开涉及形成不同类型的Cu2ZnSnS4（CZTS）太阳能电池和可以组合变化和评估的铜铟镓硒（CIGS）太阳能电池的方法。 这些方法都使用组合处理工具形成位点隔离区域，并且使用这些位置隔离区域形成太阳能电池区域。 因此，可以在单个衬底上快速形成多个太阳能电池，以用于组合方法。 可以组合地改变所描述的方法的任何单独过程以测试各种工艺条件或材料。

公开(公告)号：US08502187B2

公开(公告)日：2013-08-06

申请号：US13454392

申请日：2012-04-24

Applicant: Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

Inventor： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

IPC: H01L47/00

CPC classification number: H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

Abstract translation: 描述了包括掺杂硅电极的电阻式开关存储元件，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特之间 eV），第一电极和第二电极之间的金属氧化物层，金属氧化物层使用体积介导的开关进行开关，并且具有大于4eV的带隙，并且存储元件从低电阻状态切换到高电阻 状态，反之亦然。

公开(公告)号：US20130134373A1

公开(公告)日：2013-05-30

申请号：US13305568

申请日：2011-11-28

Applicant: Yun Wang ,  Imran Hashim ,  Tony Chiang

Inventor： Yun Wang ,  Imran Hashim ,  Tony Chiang

IPC: H01L45/00

CPC classification number: G11C13/0007 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: A nonvolatile resistive memory element has a novel variable resistance layer comprising one or more rare-earth oxides. The rare-earth oxide has a high k value, a high bandgap energy, and the ability to maintain an amorphous structure after thermal anneal processes. Thus, the novel variable resistance layer facilitates improved switching performance and reliability of the resistive memory element.

Abstract translation: 非易失性电阻存储元件具有包含一种或多种稀土氧化物的新颖的可变电阻层。 稀土氧化物具有高k值，高带隙能，以及热退火工艺后保持非晶结构的能力。 因此，新颖的可变电阻层有助于提高电阻式存储元件的开关性能和可靠性。

公开(公告)号：US20130071984A1

公开(公告)日：2013-03-21

申请号：US13236481

申请日：2011-09-19

Applicant: Yun Wang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik ,  Tony Chiang

Inventor： Yun Wang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik ,  Tony Chiang

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其具有设置在金属氧化物本体层上或其上的金属氧化物缓冲层。 金属氧化物本体层含有富金属氧化物材料，金属氧化物缓冲层含有贫金属氧化物。 由于金属氧化物本体层比金属氧化物缓冲层氧化较少或更金属，所以金属氧化物本体层的电阻小于金属氧化物缓冲层的电阻。 在一个实例中，金属氧化物本体层含有富金属氧化铪材料，金属氧化物缓冲层含有贫金属氧化锆材料。

公开(公告)号：US08369131B2

公开(公告)日：2013-02-05

申请号：US13286472

申请日：2011-11-01

Applicant: Yun Wang ,  Prashant B Phatak ,  Tony Chiang

Inventor： Yun Wang ,  Prashant B Phatak ,  Tony Chiang

IPC: G11C11/00 ,  G11C11/36

CPC classification number: G11C13/02 ,  G11C7/00 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72

Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.

公开(公告)号：US08343813B2

公开(公告)日：2013-01-01

申请号：US12705474

申请日：2010-02-12

Applicant: Ronald John Kuse ,  Imran Hashim ,  Tony Chiang

Inventor： Ronald John Kuse ,  Imran Hashim ,  Tony Chiang

IPC: H01L21/332 ,  H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1641

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

公开(公告)号：US20120315725A1

公开(公告)日：2012-12-13

申请号：US13593116

申请日：2012-08-23

Applicant: Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

Inventor： Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

IPC: H01L21/8239

CPC classification number: H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

公开(公告)号：US20120305878A1

公开(公告)日：2012-12-06

申请号：US13149528

申请日：2011-05-31

Applicant: Michael Miller ,  Prashant Phatak ,  Tony Chiang

Inventor： Michael Miller ,  Prashant Phatak ,  Tony Chiang

IPC: H01L45/00

CPC classification number: H01L45/085 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146

Abstract: A nonvolatile memory element may include, but is not limited to: a first electrode; a second electrode; and a resistive switching material disposed between the first electrode and the second electrode, wherein at least one of the first electrode or the second electrode includes at least one of a metal cation or metalloid cation having a valence state, oxidation state or oxidation number and wherein the resistive switching material includes at least one of a metal cation or a metalloid cation having the same valence state oxidation state or oxidation number as the at least one of a metal cation or metalloid cation of the at least one of the first electrode or the second electrode.

Abstract translation: 非易失性存储元件可以包括但不限于：第一电极; 第二电极; 以及设置在第一电极和第二电极之间的电阻性开关材料，其中第一电极或第二电极中的至少一个包括具有价态，氧化态或氧化数的金属阳离子或准金属阳离子中的至少一种，并且其中 电阻开关材料包括与第一电极或第二电极中的至少一个的金属阳离子或准金属阳离子中的至少一种具有相同价态氧化态或氧化数的金属阳离子或准金属阳离子中的至少一种 电极。