公开(公告)号：US20180269392A1

公开(公告)日：2018-09-20

申请号：US15705074

申请日：2017-09-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takayuki ISHIKAWA ,  Sanggyu KOH ,  Tetsu MOROOKA

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1246 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1616

Abstract: A memory device includes first interconnects extending in a first direction; a second interconnect extending in a second direction crossing the first interconnects; an insulating film provided between two first interconnects; and a resistance change film between the first interconnects and the second interconnect. The resistance change film includes a first layer and second layers, the first layer extending in the second direction along the second interconnect, and the second layers being provided selectively between the respective first interconnects and the first layer. The second layers protrude toward the second interconnect exceeding an end surface of the insulating film in a third direction from the respective first interconnects toward the second interconnect. The respective second layers have a surface on a side of the first interconnects, and a width in the second direction of the surface is wider than a width in the second direction of the first interconnect.

公开(公告)号：US20200286902A1

公开(公告)日：2020-09-10

申请号：US16518030

申请日：2019-07-22

Applicant: Toshiba Memory Corporation

Inventor： Natsuki FUKUDA ,  Satoshi NAGASHIMA ,  Tetsu MOROOKA ,  Noritaka ISHIHARA

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/06 ,  H01L21/311 ,  H01L21/764 ,  H01L21/28

Abstract: According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.

公开(公告)号：US20190088869A1

公开(公告)日：2019-03-21

申请号：US15909125

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yefei HAN ,  Tetsu MOROOKA

IPC: H01L45/00 ,  H01L27/24 ,  G11C7/06 ,  G11C7/12

CPC classification number: H01L45/06 ,  G11C7/06 ,  G11C7/12 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0033 ,  G11C29/04 ,  G11C29/70 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1608

Abstract: A memory device includes a first conductive layer and a second conductive layer. A variable resistance layer is disposed between the first conductive layer and the second conductive layer and includes a first layer containing a semiconductor or a first metal oxide, and a second layer containing a second metal oxide. A phase-change layer is disposed either between the first conductive layer and the variable resistance layer or between the second conductive layer and the variable resistance layer.

公开(公告)号：US20190296085A1

公开(公告)日：2019-09-26

申请号：US16124109

申请日：2018-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tetsu MOROOKA

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A memory device includes a first stacked structure including a plurality of first conductive layers extending in a first direction and arrayed along a second direction intersecting with the first direction, a second stacked structure provided on the first stacked structure and including a plurality of second conductive layers extending in the first direction and arrayed along the second direction, an insulating layer provided between the first and second stacked structures, a third conductive layer provided in the first stacked structure and extending in the second direction, and a fourth conductive layer provided in the second stacked structure, extending in the second direction, and including one portion and another portion located more away from the insulating layer in the second direction than the one portion, a length of the one portion in the first direction being larger than a length of the another portion in the first direction.

公开(公告)号：US20190296084A1

公开(公告)日：2019-09-26

申请号：US16123022

申请日：2018-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shota MOMBETSU ,  Akira YOTSUMOTO ,  Tetsu MOROOKA ,  Mutsumi OKAJIMA

IPC: H01L27/24 ,  G11C13/00

Abstract: A storage device includes a substrate; a plurality of insulating layers extending in a first direction; a plurality of first conductive layers extending in the first direction, and stacked alternately with the plurality of insulating layers along a second direction that intersects the first direction and is perpendicular to the substrate; a second conductive layer extending in the second direction; a recording layer provided between the second conductive layer and the plurality of first conductive layers; a first transistor electrically connected to the second conductive layer; a second transistor provided adjacent to the first transistor in a third direction that intersects the first direction and the second direction and is parallel to the substrate; and a first insulator provided on the second transistor.

公开(公告)号：US20190088318A1

公开(公告)日：2019-03-21

申请号：US15909535

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tetsu MOROOKA

IPC: G11C13/00 ,  G11C11/56

Abstract: A memory device includes: a first conductive layer extending in a first direction, and a second conductive layer extending in a second direction intersecting with the first direction. A third conductive layer is electrically connected to the second conductive layer. A variable resistance layer includes a first layer containing a semiconductor or a first metal oxide and a second layer located between the first layer and the second conductive layer and containing a second metal oxide. The second layer includes a first end and a second end spaced from the third conductive layer farther than the first end. An intermediate layer is provided between the variable resistance layer and the second conductive layer and has a resistivity higher than that of the second layer. An insulator is provided between the first end and the second conductive layer and has a resistivity higher than that of the second layer.