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公开(公告)号:US20190088720A1
公开(公告)日:2019-03-21
申请号:US15927326
申请日:2018-03-21
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Takayuki ISHIKAWA , Mutsumi OKAJIMA , Takayuki TSUKAMOTO
CPC classification number: H01L27/2463 , H01L45/06 , H01L45/146
Abstract: A storage apparatus according to embodiments includes: a first interlayer insulating film extending in a first direction; a second interlayer insulating film extending in the first direction; a first conductive layer extending in the first direction and provided between the first interlayer insulating film and the second interlayer insulating film; a second conductive layer extending in a second direction intersecting the first direction; a resistance change layer including a first portion provided between the first interlayer insulating film and the second interlayer insulating film and including a second portion provided between the second conductive layer and the first interlayer insulating film, between the second conductive layer and the first conductive layer, and between the second conductive layer and the second interlayer insulating film; and a sidewall insulating film provided between the first portion and the first interlayer insulating film and between the first portion and the second interlayer insulating film.
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公开(公告)号:US20170373119A1
公开(公告)日:2017-12-28
申请号:US15465049
申请日:2017-03-21
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Atsushi OGA , Mutsumi OKAJIMA , Natsuki FUKUDA , Takeshi YAMAGUCHI , Toshiharu TANAKA , Hiroyuki ODE
CPC classification number: H01L27/249 , H01L27/2454 , H01L45/1226 , H01L45/146 , H01L45/16
Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.
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公开(公告)号:US20190296084A1
公开(公告)日:2019-09-26
申请号:US16123022
申请日:2018-09-06
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Shota MOMBETSU , Akira YOTSUMOTO , Tetsu MOROOKA , Mutsumi OKAJIMA
Abstract: A storage device includes a substrate; a plurality of insulating layers extending in a first direction; a plurality of first conductive layers extending in the first direction, and stacked alternately with the plurality of insulating layers along a second direction that intersects the first direction and is perpendicular to the substrate; a second conductive layer extending in the second direction; a recording layer provided between the second conductive layer and the plurality of first conductive layers; a first transistor electrically connected to the second conductive layer; a second transistor provided adjacent to the first transistor in a third direction that intersects the first direction and the second direction and is parallel to the substrate; and a first insulator provided on the second transistor.
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公开(公告)号:US20180006089A1
公开(公告)日:2018-01-04
申请号:US15706598
申请日:2017-09-15
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Natsuki FUKUDA , Mutsumi OKAJIMA , Atsushi OGA , Toshiharu TANAKA , Takeshi YAMAGUCHI , Takeshi TAKAGI , Masanori KOMURA
IPC: H01L27/24 , H01L27/11582 , H01L27/11578 , H01L27/11575 , H01L27/11573 , H01L27/11556 , H01L21/311 , H01L27/11551 , H01L21/822 , H01L21/768 , H01L21/3213 , H01L29/792 , H01L27/1157
CPC classification number: H01L27/2481 , H01L21/311 , H01L21/3213 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L21/8221 , H01L23/5226 , H01L23/5329 , H01L27/0688 , H01L27/101 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/7926
Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.
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公开(公告)号:US20180069050A1
公开(公告)日:2018-03-08
申请号:US15696756
申请日:2017-09-06
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Kotaro NODA , Mutsumi OKAJIMA
CPC classification number: H01L27/249 , H01L27/2436 , H01L27/2454 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/1683
Abstract: A memory device includes a first interconnect extending in a first direction, semiconductor members extending in a second direction, a second interconnect provided between the semiconductor members and extending in a third direction, a first insulating film provided between the semiconductor member and the second interconnect, third interconnects extending in the second direction, fourth interconnects provided between the third interconnects and arranged along the second direction, a resistance change film provided between the third interconnect and the fourth interconnects, and a first film. The first film is provided between the second interconnect and the fourth interconnect, interposes between the semiconductor member and the resistance change film, and not interpose between the semiconductor member and the third interconnect connected to each other. A first end of the semiconductor member is connected to the first interconnect. The third interconnect is connected to a second end of the semiconductor member.
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