公开(公告)号：US20070021293A1

公开(公告)日：2007-01-25

申请号：US11161146

申请日：2005-07-25

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Mark Masters

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Mark Masters

IPC分类号： B01J29/04 ,  B01J29/87

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US20060169972A1

公开(公告)日：2006-08-03

申请号：US10906016

申请日：2005-01-31

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

IPC分类号： H01L29/06

CPC分类号： H01L27/0688 ,  B82Y10/00 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/0705 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/057 ,  Y10S977/938

摘要： A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor. A method of forming the inventive hybrid semiconductor structure having at least one shared node between the vertical carbon nanotube transistor and the horizontal semiconductor device is also provided.

摘要翻译： 提供一种混合半导体结构，其包括水平半导体器件和垂直碳纳米管晶体管，其中垂直碳纳米管晶体管和水平半导体器件具有至少一个共享节点。 至少一个共享节点可以包括例如FET的漏极，源极或栅极电极，或双极晶体管的发射极，集电极或基极。 还提供了形成本发明的混合半导体结构的方法，该结构在竖直碳纳米管晶体管和水平半导体器件之间具有至少一个共享节点。

公开(公告)号：US20060292861A1

公开(公告)日：2006-12-28

申请号：US11458726

申请日：2006-07-20

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

IPC分类号： H01L21/4763

CPC分类号： B82Y10/00 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

摘要翻译： 集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。 优选地，导电路径包括在导电层之间运行的通孔。 优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔 有铜的腔。 然后在通孔上形成下一导电层。

公开(公告)号：US20050286293A1

公开(公告)日：2005-12-29

申请号：US10879815

申请日：2004-06-29

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

IPC分类号： G11C11/00 ,  G11C13/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/17 ,  H01L27/108 ,  H01L27/10861 ,  H01L27/10873 ,  Y10S977/742

摘要： A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.

摘要翻译： 用于存储器电路的增益单元，由多个增益单元形成的存储器电路，以及制造这种增益单元和存储器电路的方法。 存储增益单元包括存储电容器，与存储电容器电耦合以对存储电容器进行充电和放电以定义存储的电荷的写入装置和读取装置。 读取装置包括一个或多个半导体碳纳米管，每个碳纳米管电耦合在源极和漏极之间。 每个半导体碳纳米管的一部分由读取栅极和存储电容器选通，从而调节从源极到漏极流过每个半导体碳纳米管的电流。 电流与存储电容器存储的电荷成比例。 在某些实施例中，存储器增益单元可以包括多个存储电容器。

公开(公告)号：US20060008927A1

公开(公告)日：2006-01-12

申请号：US11221118

申请日：2005-09-07

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

IPC分类号： H01L21/00

CPC分类号： H01L27/108 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

摘要翻译： 用于存储器电路的存储增益单元，由多个存储器增益单元形成的存储器电路，以及制造这种存储器增益单元和存储器电路的方法。 存储器增益单元包括能够保存存储的电荷的存储装置，写入装置和读取装置。 读取装置包括半导体材料的翅片，鳍片侧面的电隔离的第一和第二栅电极，以及形成在与第一和第二栅电极相邻的鳍片中的源极和漏极。 第一栅电极与存储装置电耦合。 第一和第二栅极电极用于选通限定在源极和漏极之间的鳍片的区域，从而调节从源极流到漏极的电流。 当门控时，电流的大小取决于存储设备存储的电量。

公开(公告)号：US20050189655A1

公开(公告)日：2005-09-01

申请号：US10787640

申请日：2004-02-26

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48

CPC分类号： B82Y10/00 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

摘要翻译： 集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。 优选地，导电路径包括在导电层之间延伸的通孔。 优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔 有铜的腔。 然后在通孔上形成下一导电层。

公开(公告)号：US20060038167A1

公开(公告)日：2006-02-23

申请号：US10711083

申请日：2004-08-20

申请人： Mark Hakey ,  Mark Masters ,  Leah Pastel ,  David Vallett

发明人： Mark Hakey ,  Mark Masters ,  Leah Pastel ,  David Vallett

IPC分类号： H01L31/072

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G01R31/2884 ,  H01L27/088 ,  H01L27/286 ,  H01L29/0673 ,  H01L29/78 ,  H01L51/0048 ,  H01L51/0512 ,  Y10S977/761 ,  Y10S977/762 ,  Y10S977/765

摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.

摘要翻译： 一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。 此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。 此外，CNT FET适用于检测集成电路内的故障电路。

公开(公告)号：US20060195285A1

公开(公告)日：2006-08-31

申请号：US10906590

申请日：2005-02-25

申请人： Pierre Bouchard ,  Mark Hakey ,  Mark Masters ,  Leah Pastel ,  James Slinkman ,  David Vallett

发明人： Pierre Bouchard ,  Mark Hakey ,  Mark Masters ,  Leah Pastel ,  James Slinkman ,  David Vallett

IPC分类号： G06F19/00

CPC分类号： G01R31/2856 ,  G01R31/2831 ,  G01R31/318511 ,  G01R31/3187

摘要： A diagnostic system and method for testing an integrated circuit (IC) during fabrication thereof, wherein the diagnostic system comprises at least one IC chip comprising an electrical signature; a sacrificial circuit adjacent to the IC chip and comprising a known electrical signature and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit indicates that the IC chip is mis-designed. The diagnostic system further comprises a semiconductor wafer comprising a plurality of IC chips and a kerf area separating one IC chip from another IC chip. The sacrificial circuit is located in the kerf area or alternatively on each of the plurality of IC chips. A mis-designed IC chip comprises abnormally functioning circuitry.

摘要翻译： 一种用于在其制造期间测试集成电路（IC）的诊断系统和方法，其中所述诊断系统包括至少一个包括电特征的IC芯片; 邻近于IC芯片的牺牲电路，包括已知的电气签名和故意错误设计的电路; 以及比较器，用于将IC芯片的电气签名与牺牲电路的已知电气签名进行比较，其中IC芯片的电子签名与牺牲电路的已知电气签名的匹配表明IC芯片是错误的 设计。 诊断系统还包括半导体晶片，其包括多个IC芯片和将IC芯片与另一IC芯片分开的切口区域。 牺牲电路位于切口区域中，或者替代地位于多个IC芯片中的每一个上。 错误设计的IC芯片包括异常功能的电路。

公开(公告)号：US20070197010A1

公开(公告)日：2007-08-23

申请号：US11696370

申请日：2007-04-04

申请人： Mark Hakey ,  Mark Masters ,  Leah Pastel ,  David Vallett

发明人： Mark Hakey ,  Mark Masters ,  Leah Pastel ,  David Vallett

IPC分类号： H01L21/3205

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G01R31/2884 ,  H01L27/088 ,  H01L27/286 ,  H01L29/0673 ,  H01L29/78 ,  H01L51/0048 ,  H01L51/0512 ,  Y10S977/761 ,  Y10S977/762 ,  Y10S977/765

摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.

摘要翻译： 一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。 此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。 此外，CNT FET适用于检测集成电路内的故障电路。

公开(公告)号：US07503021B2

公开(公告)日：2009-03-10

申请号：US11160266

申请日：2005-06-16

申请人： Matt Boucher ,  John M. Cohn ,  Richard Dauphin ,  Mark Masters ,  Judith H. McCullen ,  Sarah C. Braasch ,  Michael H. Sitko

发明人： Matt Boucher ,  John M. Cohn ,  Richard Dauphin ,  Mark Masters ,  Judith H. McCullen ,  Sarah C. Braasch ,  Michael H. Sitko

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G01R31/3025 ,  G01R31/303

摘要： The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.

摘要翻译： 本发明提供了用于诊断集成电路的方法，系统和程序产品。 特别地，本发明为集成电路的每个相关电路层捕获一个或多个图像。 基于图像，生成组件网表。 此外，通过将分层组合规则应用于组件网表生成逻辑网表。 组件网表和/或逻辑网表可以与参考网表进行比较以诊断集成电路。 本发明还可以根据从网表确定的端口，功率和/或组件引脚连接信息，组件网络表或逻辑网表，其中组件被布置。 此外，可以以选择性地显示布线连接以辅助用户智能地布置电路部件的方式来显示原理图。