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    Semiconductor device having trench capacitor and fabrication method for the same
    3.
    发明申请
    Semiconductor device having trench capacitor and fabrication method for the same 审中-公开
    具有沟槽电容器的半导体器件及其制造方法

    公开(公告)号：US20050145914A1

    公开(公告)日：2005-07-07

    申请号：US10892496

    申请日：2004-07-16

    申请人： Toshiharu Tanaka ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kido

    发明人： Toshiharu Tanaka ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kido

    IPC分类号： H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/20 ,  H01L29/76

    CPC分类号： H01L27/10867 ,  H01L29/66181 ,  H01L29/945

    摘要： A semiconductor memory includes a semiconductor substrate; a capacitor arranged in a lower portion of the trench; a collar oxide film arranged on a side of the trench above the capacitor and having an upper collar member and a lower collar member, the upper collar member being thinner than the lower collar member so as to provide a height difference therebetween; a storage node arranged on a side of the collar oxide film; a select transistor provided on the semiconductor substrate and having a doped layer in contact with the collar oxide film; and a conductor portion arranged upon the storage node and the doped layer.

    摘要翻译： 半导体存储器包括半导体衬底; 布置在沟槽的下部的电容器; 环形氧化膜，布置在电容器上方的沟槽的一侧，并具有上衣领构件和下衣领构件，上衣领构件比下衣领构件更薄，以便在它们之间提供高度差; 布置在所述轴环氧化膜侧的存储节点; 设置在半导体衬底上并具有与环氧化膜接触的掺杂层的选择晶体管; 以及布置在存储节点和掺杂层上的导体部分。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非挥发性半导体存储器件及其制造方法

    公开(公告)号：US20080315296A1

    公开(公告)日：2008-12-25

    申请号：US12142289

    申请日：2008-06-19

    申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/115 ,  H01L27/11556

    摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

    摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

    Semiconductor memory device and manufacturing method thereof
    5.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US08659070B2

    公开(公告)日：2014-02-25

    申请号：US12561451

    申请日：2009-09-17

    申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

    发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kido ,  Masaru Kito ,  Mitsuru Sato

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7881 ,  H01L29/7926

    摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

    摘要翻译： 本发明的半导体存储器件包括具有串联连接的多个电可再编程存储器单元的多个存储器串，具有列形半导体的存储器串，形成在柱状半导体周围的第一绝缘膜，电荷累积层 形成在第一绝缘膜周围，形成在电荷累积膜周围的第二绝缘膜和围绕第二绝缘膜形成的多个电极，经由多个选择晶体管连接到存储器串的一端的位线，以及导电 分别在存储器串的多个电极和不同的存储器串的多个电极中分别共享，其中导电层的每个端部在平行于位线的方向上形成为台阶形状 。

    Non-volatile semiconductor storage device and method of manufacturing the same
    6.
    发明授权
    Non-volatile semiconductor storage device and method of manufacturing the same 有权
    非易失性半导体存储装置及其制造方法

    公开(公告)号：US08253187B2

    公开(公告)日：2012-08-28

    申请号：US12142289

    申请日：2008-06-19

    申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    IPC分类号： H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11556

    摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

    摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。