公开(公告)号：US4609933A

公开(公告)日：1986-09-02

申请号：US662080

申请日：1984-10-18

申请人： Toshihiro Nakajima ,  Yoshiaki Hisamoto ,  Kozo Yamagami

发明人： Toshihiro Nakajima ,  Yoshiaki Hisamoto ,  Kozo Yamagami

IPC分类号： H01L29/10 ,  H01L29/74 ,  H01L29/744 ,  H01L29/06

CPC分类号： H01L29/74 ,  H01L29/102 ,  H01L29/744

摘要： A gate turn-off thyristor including N-type emitter regions (4) formed in part in the surface layer of a P-type base layer (3), and P.sup.+ layer regions (10) of a high impurity concentration formed immediately beneath gate electrodes (8) in the P-type base layer (3) and immediately beneath the periphery of the N-type emitter regions (4), such that the depth of the P.sup.+ layer regions immediately beneath the gate electrodes (8) is selected to be deeper than the N-type emitter regions (4).

摘要翻译： 包括部分形成在P型基极层（3）的表面层中的N型发射极区域（4）的栅极截止晶闸管以及紧邻栅极电极形成的高杂质浓度的P +层区域（10） （3）中并且紧邻在N型发射极区域（4）的周围的下方，使得栅电极（8）正下方的P +层区域的深度被选择为 比N型发射极区域（4）更深。

公开(公告)号：US08692323B2

公开(公告)日：2014-04-08

申请号：US13308028

申请日：2011-11-30

申请人： Kazunari Hatade ,  Yoshiaki Hisamoto

发明人： Kazunari Hatade ,  Yoshiaki Hisamoto

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

摘要： A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base regions and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface.

摘要翻译： 半导体器件具有具有上主表面和下主表面的半导体衬底。 半导体衬底包括漏极层，主要基底区域，底部基底区域和源极区域。 半导体器件包括与主基极区域和源极区域连接并且不连接到底部基极区域的第一主电极，与漏极层和源极区域之间插入的主基极区域中的沟道区域相对的栅电极，其中， 设置在其间的栅绝缘膜，与上主表面中的下基板区域的暴露表面相对的导电栅极焊盘，绝缘层插入其间，导电栅极焊盘连接到栅电极，第二主电极连接 到下主表面。

公开(公告)号：US20070096166A1

公开(公告)日：2007-05-03

申请号：US11612341

申请日：2006-12-18

申请人： KAZUNARI HATADE ,  Yoshiaki Hisamoto

发明人： KAZUNARI HATADE ,  Yoshiaki Hisamoto

IPC分类号： H01L29/80

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

摘要： A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base region and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface.

摘要翻译： 半导体器件具有具有上主表面和下主表面的半导体衬底。 半导体衬底包括漏极层，主要基底区域，底部基底区域和源极区域。 半导体器件包括连接到主基极区域和源极区域并且不连接到欠底部基极区域的第一主电极，与漏极层和源极区域之间插入的主基极区域中的沟道区域相对的栅电极， 设置在其间的栅绝缘膜，与上主表面中的下基板区域的暴露表面相对的导电栅极焊盘，绝缘层插入其间，导电栅极焊盘连接到栅电极，第二主电极连接 到下主表面。

公开(公告)号：US07180106B2

公开(公告)日：2007-02-20

申请号：US10296220

申请日：2001-04-04

申请人： Kazunari Hatade ,  Yoshiaki Hisamoto

发明人： Kazunari Hatade ,  Yoshiaki Hisamoto

IPC分类号： H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

摘要： A semiconductor device has an enhanced di/dt tolerance and a dv/dt tolerance without increasing an ON resistance. An underpad base region is provided on a region in an upper main surface of a semiconductor substrate which is provided under a gate pad, and the underpad base region is not connected to a source electrode and is not coupled to a main base region connected to the source electrode. The underpad base region is brought into a floating state.

摘要翻译： 半导体器件具有增强的di / dt容差和dv / dt容限，而不增加导通电阻。 底板底部区域设置在设置在栅极焊盘下方的半导体衬底的上主表面上的区域上，并且底板基极区域未连接到源电极并且不耦合到连接到源极电极的主基极区域 源电极。 底板底座区域进入浮动状态。

公开(公告)号：US5321295A

公开(公告)日：1994-06-14

申请号：US396680

申请日：1989-08-22

申请人： Yoshiaki Hisamoto

发明人： Yoshiaki Hisamoto

IPC分类号： H01L29/68 ,  H01L29/06 ,  H01L29/41 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L27/02 ,  H01L29/10 ,  H01L29/74

CPC分类号： H01L29/4238 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/7395

摘要： An insulated gate bipolar transistor comprises an insulation film (7) formed on a channel region (6) and a gate electrode (8) formed on the insulation film (7). The end portion of the gate electrode (8) has recesses so that the gage electrode (8) covers part of the channel region (6) at a predetermined rate. The rate may be made small to increase a channel resistance so that an excessive current at the time of load short-circuiting can be suppressed. In place of the recesses, a step structure may be provided. Further the gate electrode (8) may cover part of the channel region (6) without providing the recesses.

摘要翻译： 绝缘栅双极晶体管包括形成在沟道区（6）上的绝缘膜（7）和形成在绝缘膜（7）上的栅电极。 栅电极（8）的端部具有凹部，使得规定电极（8）以预定的速率覆盖沟道区域（6）的一部分。 可以使速率变小以增加通道电阻，从而可以抑制负载短路时的过电流。 代替凹部，可以提供台阶结构。 此外，栅极电极（8）可以覆盖沟道区域（6）的一部分而不设置凹部。

公开(公告)号：US08274095B2

公开(公告)日：2012-09-25

申请号：US13118719

申请日：2011-05-31

申请人： Yoshiaki Hisamoto

发明人： Yoshiaki Hisamoto

IPC分类号： H01L29/739

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/66333 ,  Y10S257/901

摘要： A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 μm, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 μm. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 μm as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.

摘要翻译： 具有本发明的高耐压功率器件IGBT的半导体器件具有在背面ap集电极层上，硼的注入量约为3×1013 / cm2，能量约为50KeV，深度约为0.5μm， n +缓冲层，磷的注入量为约3×10 12 / cm 2，能量为120KeV，深度约为20μm。 为了控制寿命，半导体衬底暴露于背面的质子。 最佳地，从后表面测量，以大约1×1011 / cm 2的剂量将质子暴露于约32μm的深度。 因此，可以消除快速恢复现象，并且可以实现改进的低饱和电压（Vce（sat）） - 偏移电压（Eoff）权衡。

公开(公告)号：US20090014753A1

公开(公告)日：2009-01-15

申请号：US11937725

申请日：2007-11-09

申请人： Yoshiaki Hisamoto ,  Atsushi Narazaki ,  Hitoshi Uemura

发明人： Yoshiaki Hisamoto ,  Atsushi Narazaki ,  Hitoshi Uemura

IPC分类号： H01L29/00 ,  H01L21/425

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/402

摘要： A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.

摘要翻译： 本发明的功率半导体器件具有有源区和电场还原区，包括：第一导电型的发射极区; 与发射极区域接触的第二导电类型的基极区域; 所述第一导电类型的电强度提供区域与所述基极区域接触; 与所述电强度提供区域接触的所述第二导电类型的集电极区域; 以及与集电极区域接触的集电极; 其特征在于，所述集电极区域配置在各自含有所述第二导电型掺杂剂的有源区域和电场还原区域上，并且设置在所述电场还原区域上的所述集电极区域包括具有较低密度的载流子的区域， 导电类型比设置在有源区上的集电极区域。

公开(公告)号：US20120080744A1

公开(公告)日：2012-04-05

申请号：US13308028

申请日：2011-11-30

申请人： Kazunari HATADE ,  Yoshiaki Hisamoto

发明人： Kazunari HATADE ,  Yoshiaki Hisamoto

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

摘要： A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base regions and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface.

摘要翻译： 半导体器件具有具有上主表面和下主表面的半导体衬底。 半导体衬底包括漏极层，主要基底区域，底部基底区域和源极区域。 半导体器件包括与主基极区域和源极区域连接并且不连接到底部基极区域的第一主电极，与漏极层和源极区域之间插入的主基极区域中的沟道区域相对的栅电极，其中， 设置在其间的栅绝缘膜，与上主表面中的下基板区域的暴露表面相对的导电栅极焊盘，绝缘层插入其间，导电栅极焊盘连接到栅电极，第二主电极连接 到下主表面。

公开(公告)号：US06580121B2

公开(公告)日：2003-06-17

申请号：US09953281

申请日：2001-09-17

申请人： Yoshiaki Hisamoto

发明人： Yoshiaki Hisamoto

IPC分类号： H01L2976

CPC分类号： H01L29/7811 ,  H01L27/0629 ,  H01L29/7808 ,  H01L29/7813 ,  H01L29/866 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2924/00

摘要： A Zener diode is provided in a chip periphery portion which entirely surrounds at a periphery a unit cell portion and a gate pad portion along first to fourth directions. The Zener diode has an N+-P-N+-P-N+ structure consisting of an N+ type layer, a P type layer, an N+ type layer, a P type layer, and an N+ type layer, in which these layers extend along the first to fourth directions. With this structure, a power semiconductor device achieves a higher electrostatic strength by (1) a reduction in on-state resistance through enlargement of an effective cell region by downsizing the gate pad, and (2) an improvement in current-voltage characteristic of the Zener diode through an increase in PN junction width.

摘要翻译： 齐纳二极管设置在芯片周边部分中，其沿着第一至第四方向在单元单元部分和栅极焊盘部分的周围完全包围。 齐纳二极管具有由N +型层，P型层，N +型层，P型层和N +型层构成的N + -P-N + -P-N +结构，其中这些层沿着 第一到第四个方向。 利用这种结构，功率半导体器件通过（1）通过小型化栅极板扩大有效单元区域来降低导通电阻来实现更高的静电强度，和（2）提高电流 - 电压特性 齐纳二极管通过增加PN结宽度。

公开(公告)号：US5545573A

公开(公告)日：1996-08-13

申请号：US450778

申请日：1995-05-25

申请人： Atsushi Narazaki ,  Yoshiaki Hisamoto

发明人： Atsushi Narazaki ,  Yoshiaki Hisamoto

IPC分类号： H01L21/302 ,  H01L21/306 ,  H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7802

摘要： In order to prevent an etch-down phenomenon in a gate electrode (106), a source electrode (108) is connected to an upper major surface of a semiconductor substrate (160) through openings (112, 112a) of a protective film (107), while a gate wire (109) is connected to the gate electrode (106) through an opening (111). The opening (112, 112a) are formed by dry etching, whereby the source electrode (108) is reliably insulated from the gate electrode (106). On the other hand, the opening (111) is formed by wet etching, whereby the gate electrode (106) is not etched down. Thus, it is possible to prevent short-circuiting defectiveness across the gate electrode (106) and the semiconductor substrate (160) resulting from an etch-down phenomenon of the gate electrode (106) while guaranteeing electrical insulation between the gate electrode (106) and the source electrode (108).

摘要翻译： 为了防止栅电极（106）中的蚀刻现象，源电极（108）通过保护膜（107）的开口（112,112a）连接到半导体衬底（160）的上主表面 ），而栅极线（109）通过开口（111）连接到栅电极（106）。 通过干蚀刻形成开口（112,112a），由此源电极（108）可靠地与栅电极（106）绝缘。 另一方面，通过湿蚀刻形成开口（111），由此栅电极（106）不被蚀刻。 因此，可以防止由栅极电极（106）的蚀刻现象导致的栅电极（106）和半导体衬底（160）之间的短路缺陷，同时保证栅电极（106） 和源电极（108）。