公开(公告)号：US20090014753A1

公开(公告)日：2009-01-15

申请号：US11937725

申请日：2007-11-09

申请人： Yoshiaki Hisamoto ,  Atsushi Narazaki ,  Hitoshi Uemura

发明人： Yoshiaki Hisamoto ,  Atsushi Narazaki ,  Hitoshi Uemura

IPC分类号： H01L29/00 ,  H01L21/425

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/402

摘要： A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.

摘要翻译： 本发明的功率半导体器件具有有源区和电场还原区，包括：第一导电型的发射极区; 与发射极区域接触的第二导电类型的基极区域; 所述第一导电类型的电强度提供区域与所述基极区域接触; 与所述电强度提供区域接触的所述第二导电类型的集电极区域; 以及与集电极区域接触的集电极; 其特征在于，所述集电极区域配置在各自含有所述第二导电型掺杂剂的有源区域和电场还原区域上，并且设置在所述电场还原区域上的所述集电极区域包括具有较低密度的载流子的区域， 导电类型比设置在有源区上的集电极区域。

公开(公告)号：US5545573A

公开(公告)日：1996-08-13

申请号：US450778

申请日：1995-05-25

申请人： Atsushi Narazaki ,  Yoshiaki Hisamoto

发明人： Atsushi Narazaki ,  Yoshiaki Hisamoto

IPC分类号： H01L21/302 ,  H01L21/306 ,  H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7802

摘要： In order to prevent an etch-down phenomenon in a gate electrode (106), a source electrode (108) is connected to an upper major surface of a semiconductor substrate (160) through openings (112, 112a) of a protective film (107), while a gate wire (109) is connected to the gate electrode (106) through an opening (111). The opening (112, 112a) are formed by dry etching, whereby the source electrode (108) is reliably insulated from the gate electrode (106). On the other hand, the opening (111) is formed by wet etching, whereby the gate electrode (106) is not etched down. Thus, it is possible to prevent short-circuiting defectiveness across the gate electrode (106) and the semiconductor substrate (160) resulting from an etch-down phenomenon of the gate electrode (106) while guaranteeing electrical insulation between the gate electrode (106) and the source electrode (108).

摘要翻译： 为了防止栅电极（106）中的蚀刻现象，源电极（108）通过保护膜（107）的开口（112,112a）连接到半导体衬底（160）的上主表面 ），而栅极线（109）通过开口（111）连接到栅电极（106）。 通过干蚀刻形成开口（112,112a），由此源电极（108）可靠地与栅电极（106）绝缘。 另一方面，通过湿蚀刻形成开口（111），由此栅电极（106）不被蚀刻。 因此，可以防止由栅极电极（106）的蚀刻现象导致的栅电极（106）和半导体衬底（160）之间的短路缺陷，同时保证栅电极（106） 和源电极（108）。

公开(公告)号：US08742474B2

公开(公告)日：2014-06-03

申请号：US11937725

申请日：2007-11-09

申请人： Yoshiaki Hisamoto ,  Atsushi Narazaki ,  Hitoshi Uemura

发明人： Yoshiaki Hisamoto ,  Atsushi Narazaki ,  Hitoshi Uemura

IPC分类号： H01L29/66

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/402

摘要： A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.

摘要翻译： 本发明的功率半导体器件具有有源区和电场还原区，包括：第一导电型的发射极区; 与发射极区域接触的第二导电类型的基极区域; 所述第一导电类型的电强度提供区域与所述基极区域接触; 与所述电强度提供区域接触的所述第二导电类型的集电极区域; 以及与集电极区域接触的集电极; 其特征在于，所述集电极区域配置在各自含有所述第二导电型掺杂剂的有源区域和电场还原区域上，并且设置在所述电场还原区域上的所述集电极区域包括具有较低密度的载流子的区域， 导电类型比设置在有源区上的集电极区域。

公开(公告)号：US20090072268A1

公开(公告)日：2009-03-19

申请号：US12020959

申请日：2008-01-28

申请人： Kenji Hatori ,  Atsushi Narazaki

发明人： Kenji Hatori ,  Atsushi Narazaki

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7816

摘要： A semiconductor device includes a semiconductor substrate having a main surface and a semiconductor element having an insulated gate field effect portion formed in the semiconductor substrate. The semiconductor element includes an n− region, an n-type source region, a p-type base region, an n+ region, and a gate electrode. The n− region and the n-type source region are formed in the main surface. The p-type base region is formed in the main surface adjacent to the n-type source region. The n+ region is formed in the main surface adjacent to the p-type base region and opposed to the n-type source region with the p-type base region being interposed, and has an impurity concentration higher than the n− region. The n− region is formed in the main surface adjacent to the p-type base region and to the n+ region.

摘要翻译： 半导体器件包括具有主表面的半导体衬底和形成在半导体衬底中的具有绝缘栅场效应部分的半导体元件。 半导体元件包括n区，n型源极区，p型基极区域，n +区域和栅电极。 在主表面上形成n区和n型源极区。 p型基极区域形成在与n型源极区域相邻的主表面上。 在与p型基极区相邻的主表面上形成n +区，与插入有p型基极区的n型源极区相比，具有比n区高的杂质浓度。 n区形成在与p型基区相邻的主表面和n +区中。

公开(公告)号：US06285058B1

公开(公告)日：2001-09-04

申请号：US09485702

申请日：2000-02-28

申请人： Atsushi Narazaki ,  Hidetoshi Souno ,  Yasunori Yamashita

发明人： Atsushi Narazaki ,  Hidetoshi Souno ,  Yasunori Yamashita

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

摘要： The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to an improvement for enhancing a gate breakdown voltage. In order to achieve the object, gate wirings (9), (10) and (13) are provided to keep away from an upper end (UE) of an edge of a gate trench (6) along its longitudinal direction. More specifically, the gate wiring (9) coupled integrally with an upper surface of a gate electrode (7) is formed apart from the upper end (UE) and the gate wiring (10) is formed on an insulating film (4) also apart from the upper end (UE). The two gate wirings (9) and (10) are connected to each other through the gate wiring (13) formed on a BPSG layer (11). Moreover, an upper face of the gate electrode (7) is positioned on the same level as an upper main surface of a semiconductor substrate (90) or therebelow in the vicinity of the upper end (UE). Consequently, a concentration of an electric field generated in insulating films (8) and (17) covering the upper end (UE) can be relieved or eliminated.

摘要翻译： 绝缘栅半导体器件及其制造方法技术领域本发明涉及绝缘栅半导体器件及其制造方法，更具体地，涉及提高栅极击穿电压的改进。 为了实现该目的，提供了栅极布线（9），（10）和（13）以沿着其纵向方向远离栅极沟槽（6）的边缘的上端（UE）。 更具体地，与栅电极（7）的上表面一体地结合的栅极布线（9）形成为与上端（UE）分开，并且栅极布线（10）也形成在也分开的绝缘膜（4）上 来自上端（UE）。 两个栅极布线（9）和（10）通过形成在BPSG层（11）上的栅极布线（13）相互连接。 此外，栅电极（7）的上表面位于与半导体衬底（90）的上​​主表面或其上端附近相同的高度。 因此，可以减轻或消除在覆盖上端（UE）的绝缘膜（8）和（17）中产生的电场的浓度。

公开(公告)号：US20120309117A1

公开(公告)日：2012-12-06

申请号：US13358868

申请日：2012-01-26

申请人： Yuichiro SUZUKI ,  Atsushi Narazaki ,  Yoshiaki Terasaki

发明人： Yuichiro SUZUKI ,  Atsushi Narazaki ,  Yoshiaki Terasaki

IPC分类号： H01L21/66

CPC分类号： H01L29/0847 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/7397 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/0781 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device wherein a semiconductor element is sealed with mold resin, a MOS structure is on an upper side of the semiconductor chip, and a PN junction region is on a back side of the semiconductor chip, comprises: obtaining an in-plane distribution of impurity concentration of the PN junction region in the semiconductor chip before encapsulation so that an in-plane distribution of breakdown voltage and leakage current of the semiconductor chip become uniform after encapsulation; forming the PN junction region having the obtained in-plane distribution of impurity concentration on the back side of the semiconductor chip; and sealing the semiconductor chip with the resin after forming the PN junction region.

摘要翻译： 一种半导体器件的制造方法，其中半导体元件用模制树脂密封，MOS结构位于半导体芯片的上侧，并且PN结区域位于半导体芯片的背面，包括： 在封装之前在半导体芯片中的PN结区域的杂质浓度的平面分布，使得在封装之后半导体芯片的击穿电压和漏电流的面内分布变得均匀; 在半导体芯片的背面上形成具有所获得的杂质浓度的面内分布的PN结区域; 并在形成PN结区域之后用树脂密封半导体芯片。

公开(公告)号：US07741655B2

公开(公告)日：2010-06-22

申请号：US12020959

申请日：2008-01-28

申请人： Kenji Hatori ,  Atsushi Narazaki

发明人： Kenji Hatori ,  Atsushi Narazaki

IPC分类号： H01L29/739

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7816

摘要： A semiconductor device includes a semiconductor substrate having a main surface and a semiconductor element having an insulated gate field effect portion formed in the semiconductor substrate. The semiconductor element includes an n− region, an n-type source region, a p-type base region, an n+ region, and a gate electrode. The n− region and the n-type source region are formed in the main surface. The p-type base region is formed in the main surface adjacent to the n-type source region. The n+ region is formed in the main surface adjacent to the p-type base region and opposed to the n-type source region with the p-type base region being interposed, and has an impurity concentration higher than the n− region. The n− region is formed in the main surface adjacent to the p-type base region and to the n+ region.

摘要翻译： 半导体器件包括具有主表面的半导体衬底和形成在半导体衬底中的具有绝缘栅场效应部分的半导体元件。 半导体元件包括n区，n型源极区，p型基极区域，n +区域和栅电极。 在主表面上形成n区和n型源极区。 p型基极区域形成在与n型源极区域相邻的主表面上。 在与p型基极区相邻的主表面上形成n +区，与插入有p型基极区的n型源极区相比，具有比n区高的杂质浓度。 n区形成在与p型基区相邻的主表面和n +区中。

公开(公告)号：US07319264B2

公开(公告)日：2008-01-15

申请号：US11276668

申请日：2006-03-09

申请人： Atsushi Narazaki

发明人： Atsushi Narazaki

IPC分类号： H01L29/00 ,  H01L27/102 ,  H01L27/082 ,  H01L29/70 ,  H01L23/50

CPC分类号： H01L23/482 ,  H01L23/4824 ,  H01L23/49562 ,  H01L24/34 ,  H01L24/37 ,  H01L24/73 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/45124 ,  H01L2224/48463 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device has a structure capable of connecting a lead terminal directly to an electrode on a front surface thereof. The semiconductor device includes a first main electrode provided on the front surface, a second main electrode provided on a back surface, and a metal film provided so as to cover at least a portion of a surface of the first main electrode and for soldering the lead terminal thereto. Here, the metal film includes a plurality of opening portions through which the surface of the first main electrode is exposed.

摘要翻译： 半导体器件具有能够将引线端子直接连接到其表面上的电极的结构。 半导体器件包括设置在前表面的第一主电极，设置在背面上的第二主电极和设置成覆盖第一主电极表面的至少一部分并用于焊接引线的金属膜 终端。 这里，金属膜包括第一主电极的表面露出的多个开口部。

公开(公告)号：US06495863B2

公开(公告)日：2002-12-17

申请号：US09883201

申请日：2001-06-19

申请人： Atsushi Narazaki

发明人： Atsushi Narazaki

IPC分类号： H01L2974

CPC分类号： H01L29/66106 ,  H01L24/05 ,  H01L27/0255 ,  H01L29/7808 ,  H01L29/866 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/48

摘要： An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.

摘要翻译： 设置在用于布置齐纳二极管的区域上的绝缘体膜具有多个凹槽部分，其连续地布置在形成二极管的每个半导体区域的延伸方向D1上。 每个沟槽部分在每个半导体区域的宽度方向D2上延伸，并且具有深度T3。 每个半导体区域布置在绝缘膜的上表面上。 因此，每个半导体区域具有沿着延伸方向D1布置的多个不规则形状，并且齐纳二极管不仅在横向方向D1上而且在垂直方向D3上具有周长，使得pn结面积 在齐纳二极管中增加。 因此，为了改善二极管的栅极绝缘膜保护功能，降低了输入保护齐纳二极管的寄生电阻。

公开(公告)号：US08884383B2

公开(公告)日：2014-11-11

申请号：US13272512

申请日：2011-10-13

申请人： Atsushi Narazaki

发明人： Atsushi Narazaki

IPC分类号： H01L29/84 ,  H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L22/14 ,  G01L1/18 ,  G01L5/0047 ,  G01R31/2884 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/014 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor chip with a gate electrode, and a stress detecting element placed on a surface of the semiconductor chip, and which detects stress applied to the surface. The semiconductor device controls a control signal to be applied to the gate electrode in response to stress detected by the stress detecting element. The stress detecting element is preferably provided as a first stress detecting element which detects stress applied to a central portion of the semiconductor chip in plan view. The stress detecting element is preferably provided as a second stress detecting element which detects stress applied to a circumferential portion of the semiconductor chip in plan view.

摘要翻译： 半导体器件包括具有栅电极的半导体芯片和放置在半导体芯片的表面上的应力检测元件，并且检测施加到表面的应力。 半导体器件响应于由应力检测元件检测到的应力来控制施加到栅电极的控制信号。 应力检测元件优选地设置为在平面图中检测施加到半导体芯片的中心部分的应力的第一应力检测元件。 应力检测元件优选地设置为在平面图中检测施加到半导体芯片的圆周部分的应力的第二应力检测元件。