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18 条记录 (耗时 0.02 秒)

    Design layout preparing method
    3.
    发明授权
    Design layout preparing method 有权
    设计布局准备方法

    公开(公告)号：US07194704B2

    公开(公告)日：2007-03-20

    申请号：US11012491

    申请日：2004-12-16

    申请人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

    发明人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

    IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F9/455

    CPC分类号： G06F17/5081 ,  H01L21/0271

    摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.

    摘要翻译： 公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点 相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分 在维修准则上。

    Flip-flop circuit for capturing input signals in priority order
    5.
    发明授权
    Flip-flop circuit for capturing input signals in priority order 有权

    公开(公告)号：US07117412B2

    公开(公告)日：2006-10-03

    申请号：US10109405

    申请日：2002-03-28

    申请人： Ryuji Ogawa ,  Toshiki Morimoto

    发明人： Ryuji Ogawa ,  Toshiki Morimoto

    IPC分类号： G01R31/028 ,  H03K3/289

    CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/35625

    摘要： A flip-flop circuit includes first and second logic gates, a first selection circuit and a latch circuit. The first logic gate executes a logic operation on a first data signal and a first control signal. The second logic gate executes a logic operation on a second data signal and the first control signal. The operation results of the first and second logic gates are forcibly fixed to a predetermined value irrespective of the first and second data signals, if the first control signal is asserted. A first selection circuit selects one of the operation results of the first and second logic gates, and outputs the selected operation result as a first selection signal. A latch circuit latches the first selection signal.

    METHOD FOR PRODUCING OPTICALLY ACTIVE TRANS-2-AMINOCYCLOHEXANOL AND INTERMEDIATE OF OPTICALLY ACTIVE TRANS-2-AMINOCYCLOHEXANOL
    6.
    发明申请
    METHOD FOR PRODUCING OPTICALLY ACTIVE TRANS-2-AMINOCYCLOHEXANOL AND INTERMEDIATE OF OPTICALLY ACTIVE TRANS-2-AMINOCYCLOHEXANOL 审中-公开
    用于生产光学活性的反式-2-氨基环己醇的方法和光学活性的转移-2-氨基环己醇的中间体

    公开(公告)号：US20100185012A1

    公开(公告)日：2010-07-22

    申请号：US12664164

    申请日：2008-06-18

    申请人： Ryuji Ogawa ,  Toshihiro Fujino ,  Kenichi Sakai

    发明人： Ryuji Ogawa ,  Toshihiro Fujino ,  Kenichi Sakai

    IPC分类号： C07C59/64 ,  C07C209/88

    CPC分类号： C07B57/00 ,  C07B2200/07 ,  C07C51/02 ,  C07C51/412 ,  C07C59/64 ,  C07C213/10 ,  C07C215/44 ,  C07C2601/14

    摘要： A method of producing optically active trans-2-aminocyclohexanol includes allowing racemic trans-2-aminocyclohexanol to react with optically active 2-methoxyphenylacetic acid to produce an optically active 2-methoxyphenylacetic acid salt of optically active trans-2-aminocyclohexanol and separating the salt. An optically active 2-methoxyphenylacetic acid salt of optically active trans-2-aminocyclohexanol is also provided. The method makes it possible to produce optically active trans-2-aminocyclohexanol with ease and a high yield from an industrially-advantageous, inexpensive raw material.

    摘要翻译： 制备光学活性的反式-2-氨基环己醇的方法包括使外消旋的反式-2-氨基环己醇与光学活性的2-甲氧基苯基乙酸反应以产生光学活性的反式-2-氨基环己醇的光学活性2-甲氧基苯基乙酸盐，并将盐 。 还提供光学活性的反式-2-氨基环己醇的光学活性2-甲氧基苯基乙酸盐。 该方法可以从工业上有利的廉价原料中容易地和高收率地制备光学活性的反式-2-氨基环己醇。

    Pattern data creating method, pattern data creating program, and semiconductor device manufacturing method
    7.
    发明授权
    Pattern data creating method, pattern data creating program, and semiconductor device manufacturing method 有权
    图案数据创建方法，图案数据创建程序和半导体器件制造方法

    公开(公告)号：US08234596B2

    公开(公告)日：2012-07-31

    申请号：US12552010

    申请日：2009-09-01

    申请人： Ryuji Ogawa ,  Masahiro Miyairi ,  Shimon Maeda ,  Suigen Kyoh ,  Satoshi Tanaka

    发明人： Ryuji Ogawa ,  Masahiro Miyairi ,  Shimon Maeda ,  Suigen Kyoh ,  Satoshi Tanaka

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.

    摘要翻译： 根据本发明的实施例的图形数据创建方法包括：使用通过应用过程模拟获得的第一结果来提取边缘误差模式以基于评估目标单元图案来屏蔽图案数据，将过程模拟应用于基于 通过将周边环境图案布置在边缘误差图案中，使得通过创建掩模图案数据获得的第二结果和对掩模图案数据应用处理模拟而得到的第一结果比第一结果更差，从而产生具有周边环境图案的评估对象单元图案， 以及当存在致命错误时，基于评估对象单元图案来校正评估对象单元格图案或掩模图案数据。

    Pattern verification method, program thereof, and manufacturing method of semiconductor device
    8.
    发明申请
    Pattern verification method, program thereof, and manufacturing method of semiconductor device 失效
    模式验证方法，程序以及半导体器件的制造方法

    公开(公告)号：US20100031224A1

    公开(公告)日：2010-02-04

    申请号：US12585073

    申请日：2009-09-02

    申请人： Ryuji Ogawa ,  Koji Hashimoto

    发明人： Ryuji Ogawa ,  Koji Hashimoto

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern.

    摘要翻译： 集成电路图案的验证方法包括提取不大于预设图案尺寸的图案，从提取的图案中提取作为光刻仿真的目标的图案边缘，以及对提取的图案边缘进行光刻模拟以验证 集成电路图案。

    Pattern verification method, program thereof, and manufacturing method of semiconductor device
    9.
    发明授权
    Pattern verification method, program thereof, and manufacturing method of semiconductor device 失效
    模式验证方法，程序以及半导体器件的制造方法

    公开(公告)号：US08127265B2

    公开(公告)日：2012-02-28

    申请号：US13067567

    申请日：2011-06-09

    申请人： Ryuji Ogawa ,  Koji Hashimoto

    发明人： Ryuji Ogawa ,  Koji Hashimoto

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern.

    摘要翻译： 集成电路图案的验证方法包括提取不大于预设图案尺寸的图案，从提取的图案中提取作为光刻仿真的目标的图案边缘，以及对提取的图案边缘进行光刻模拟以验证 集成电路图案。