公开(公告)号：US20120190215A1

公开(公告)日：2012-07-26

申请号：US13189648

申请日：2011-07-25

申请人： Toshiyuki IKEUCHI ,  Pao-Hwa Chou ,  Kazuya Yamamoto ,  Kentaro Sera

发明人： Toshiyuki IKEUCHI ,  Pao-Hwa Chou ,  Kazuya Yamamoto ,  Kentaro Sera

IPC分类号： H01L21/31 ,  C23C16/46

CPC分类号： H01L21/0228 ,  C23C16/401 ,  C23C16/45546 ,  C23C16/45557 ,  H01L21/02164 ,  H01L21/02219

摘要： A disclosed film deposition method comprises alternately repeating an adsorption step and a reaction step with an interval period therebetween. The adsorption step includes opening a first on-off valve of a source gas supplying system for a predetermined time period thereby to supply a source gas to a process chamber, closing the first valve after the predetermined time period elapses, and confining the source gas within the process tube, thereby allowing the source gas to be adsorbed on an object to be processed, while a third on-off valve of a vacuum evacuation system is closed. The reaction step includes opening a second on-off valve of a reaction gas supplying system thereby to supply a reaction gas to the process chamber, thereby allowing the source gas and the reaction gas to react with each other thereby to produce a thin film on the object to be processed.

摘要翻译： 所公开的膜沉积方法包括以间隔期交替地重复吸附步骤和反应步骤。 吸附步骤包括打开源气体供应系统的第一开关阀预定时间段，从而将源气体供应到处理室，在经过预定时间段之后关闭第一阀门，并将源气体限制在 处理管，从而允许源气体被吸附在待处理物体上，而真空排气系统的第三开关阀关闭。 反应步骤包括打开反应气体供应系统的第二开关阀，从而将反应气体提供给处理室，从而使源气体和反应气体彼此反应，从而在其上产生薄膜 对象被处理。

公开(公告)号：US08658247B2

公开(公告)日：2014-02-25

申请号：US13189648

申请日：2011-07-25

申请人： Toshiyuki Ikeuchi ,  Pao-Hwa Chou ,  Kazuya Yamamoto ,  Kentaro Sera

发明人： Toshiyuki Ikeuchi ,  Pao-Hwa Chou ,  Kazuya Yamamoto ,  Kentaro Sera

IPC分类号： C23C16/40

CPC分类号： H01L21/0228 ,  C23C16/401 ,  C23C16/45546 ,  C23C16/45557 ,  H01L21/02164 ,  H01L21/02219

摘要： A disclosed film deposition method comprises alternately repeating an adsorption step and a reaction step with an interval period therebetween. The adsorption step includes opening a first on-off valve of a source gas supplying system for a predetermined time period thereby to supply a source gas to a process chamber, closing the first valve after the predetermined time period elapses, and confining the source gas within the process tube, thereby allowing the source gas to be adsorbed on an object to be processed, while a third on-off valve of a vacuum evacuation system is closed. The reaction step includes opening a second on-off valve of a reaction gas supplying system thereby to supply a reaction gas to the process chamber, thereby allowing the source gas and the reaction gas to react with each other thereby to produce a thin film on the object to be processed.

摘要翻译： 所公开的膜沉积方法包括以间隔期交替地重复吸附步骤和反应步骤。 吸附步骤包括打开源气体供应系统的第一开关阀预定时间段，从而将源气体供应到处理室，在经过预定时间段之后关闭第一阀门，并将源气体限制在 处理管，从而允许源气体被吸附在待处理物体上，而真空排气系统的第三开关阀关闭。 反应步骤包括打开反应气体供应系统的第二开关阀，从而将反应气体提供给处理室，从而使源气体和反应气体彼此反应，从而在其上产生薄膜 对象被处理。

公开(公告)号：US20070262374A1

公开(公告)日：2007-11-15

申请号：US11878296

申请日：2007-07-23

申请人： Masahiko Higashi ,  Manabu Nakamura ,  Kentaro Sera ,  Hiroyuki Nansei ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

发明人： Masahiko Higashi ,  Manabu Nakamura ,  Kentaro Sera ,  Hiroyuki Nansei ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02252 ,  H01L21/28282 ,  H01L21/31155 ,  H01L21/3185 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

摘要： After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.

公开(公告)号：US20080316790A1

公开(公告)日：2008-12-25

申请号：US12130577

申请日：2008-05-30

申请人： Fumihiko Inoue ,  Kentaro Sera

发明人： Fumihiko Inoue ,  Kentaro Sera

IPC分类号： G11C17/00 ,  H01L21/82

CPC分类号： G11C17/10 ,  H01L27/112 ,  H01L27/11226

摘要： The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality of semiconductor chips 12 by using the program head 80.

摘要翻译： 本发明是一种半导体器件的制造方法，具有以下步骤： 将具有对应于设置在半导体晶片中的多个半导体芯片的区域12中的每个OTP-ROM单元阵列21的程序点阵列的程序头80对准到要在其中的一个区域中的OTP-ROM单元阵列21 多个半导体芯片12; 并且通过使用程序头80，对于作为多个半导体芯片12的每个区域，以不同的模式对OTP-ROM单元阵列21进行编程。

公开(公告)号：US07253046B2

公开(公告)日：2007-08-07

申请号：US11065305

申请日：2005-02-25

申请人： Masahiko Higashi ,  Manabu Nakamura ,  Kentaro Sera ,  Hiroyuki Nansei ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

发明人： Masahiko Higashi ,  Manabu Nakamura ,  Kentaro Sera ,  Hiroyuki Nansei ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

IPC分类号： H01L21/8238

CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02252 ,  H01L21/28282 ,  H01L21/31155 ,  H01L21/3185 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

摘要： After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.

摘要翻译： 在通过使用具有径向线槽天线的等离子体处理器通过等离子体氮化方法形成的氮化硅膜（22）夹在氧化硅膜（21），（23）上的ONO膜之后，位线扩散层（17） ）通过离子注入形成在存储单元阵列区域（11）中，作为抗蚀剂图案（16）作为掩模，然后通过进一步的离子注入向氮化硅膜（22）提供晶格缺陷。 因此，可以实现在低温条件下形成高质量氮化物膜的高度可靠的半导体存储器件，此外，氮化物膜可以用作具有充分适应于 小型化和高度一体化是最近的需求。

公开(公告)号：US20050212074A1

公开(公告)日：2005-09-29

申请号：US11065307

申请日：2005-02-25

申请人： Kentaro Sera ,  Hiroyuki Nansei ,  Manabu Nakamura ,  Masahiko Higashi ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

发明人： Kentaro Sera ,  Hiroyuki Nansei ,  Manabu Nakamura ,  Masahiko Higashi ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/76235

摘要： A trench (4) is formed in a semiconductor substrate (1), and then a plasma oxynitride film (5) is formed on a side wall surface and a bottom surface of the trench (4) at a temperature of approximately 300° C. to 650° C. At such a temperature, no outward diffusion of impurities from the semiconductor substrate (1) occurs. Therefore, any problems such as formation of a parasitic transistor hardly occur even when ions of impurities are not implanted thereafter. After the plasma oxynitride film (5) is formed, it is thermally oxidized, and a portion where the outermost surface of the semiconductor substrate (1) meets the wall surface of the trench (4) is turned into a curved surface. As a result, the outermost surface of the semiconductor substrate (1) and the wall surface of the trench (4) meet each other while forming a curved surface, and hence a parasitic transistor is hardly formed at this portion. Consequently, formation of a hump is prevented, thereby achieving favorable characteristics.

摘要翻译： 在半导体衬底（1）中形成沟槽（4），然后在约300℃的温度下在沟槽（4）的侧壁表面和底表面上形成等离子体氧氮化物膜（5） 到650℃。在这样的温度下，不会发生杂质从半导体衬底（1）的向外扩散。 因此，即使其后没有植入杂质的离子，也难以形成诸如形成寄生晶体管的问题。 在形成等离子体氮氧化物膜（5）之后，其被热氧化，并且半导体衬底（1）的最外表面与沟槽（4）的壁表面相交的部分变成弯曲表面。 结果，半导体衬底（1）的最外表面和沟槽（4）的壁表面在形成弯曲表面的同时彼此相遇，因此在该部分难以形成寄生晶体管。 因此，防止形成隆起，从而获得有利的特性。

公开(公告)号：US08815652B2

公开(公告)日：2014-08-26

申请号：US12130577

申请日：2008-05-30

申请人： Fumihiko Inoue ,  Kentaro Sera

发明人： Fumihiko Inoue ,  Kentaro Sera

IPC分类号： H01L21/82 ,  H01L27/112 ,  G11C17/10

CPC分类号： G11C17/10 ,  H01L27/112 ,  H01L27/11226

摘要： The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality of semiconductor chips 12 by using the program head 80.

摘要翻译： 本发明是一种半导体器件的制造方法，具有以下步骤： 将具有对应于设置在半导体晶片中的多个半导体芯片的区域12中的每个OTP-ROM单元阵列21的程序点阵列的程序头80对准到要在其中的一个区域中的OTP-ROM单元阵列21 多个半导体芯片12; 并且通过使用程序头80，对于作为多个半导体芯片12的每个区域，以不同的模式对OTP-ROM单元阵列21进行编程。

公开(公告)号：US20060228899A1

公开(公告)日：2006-10-12

申请号：US11441237

申请日：2006-05-26

申请人： Hiroyuki Nansei ,  Manabu Nakamura ,  Kentaro Sera ,  Masahiko Higashi ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

发明人： Hiroyuki Nansei ,  Manabu Nakamura ,  Kentaro Sera ,  Masahiko Higashi ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

IPC分类号： H01L21/31 ,  H01L21/336

CPC分类号： H01L21/0234 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/3145 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  Y10S438/954

摘要： After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.

公开(公告)号：US07098147B2

公开(公告)日：2006-08-29

申请号：US10643967

申请日：2003-08-20

申请人： Hiroyuki Nansei ,  Manabu Nakamura ,  Kentaro Sera ,  Masahiko Higashi ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

发明人： Hiroyuki Nansei ,  Manabu Nakamura ,  Kentaro Sera ,  Masahiko Higashi ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

IPC分类号： H01L21/31

CPC分类号： H01L27/11568 ,  H01L21/3145 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  Y10S438/954

摘要： After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.

摘要翻译： 在硅区域上形成下部氧化硅膜之后，通过例如热CVD法在下部氧化硅膜上形成硅膜。 随后，通过等离子体氮化方法将硅膜完全氮化，由氮化硅膜代替。 随后，通过等离子体氧化方法氧化氮化硅膜的表面层，以被上部氧化硅膜代替。 形成作为由下部氧化硅膜，氮化硅膜和上部氧化硅膜构成的多层绝缘膜的ONO膜。

公开(公告)号：US20080265309A1

公开(公告)日：2008-10-30

申请号：US12213542

申请日：2008-06-20

申请人： Masahiko Higashi ,  Manabu Nakamura ,  Kentaro Sera ,  Hiroyuki Nansei ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

发明人： Masahiko Higashi ,  Manabu Nakamura ,  Kentaro Sera ,  Hiroyuki Nansei ,  Yukihiro Utsuno ,  Hideo Takagi ,  Tatsuya Kajita

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02252 ,  H01L21/31155 ,  H01L21/3185 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/66833

摘要： After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.

摘要翻译： 在通过使用具有径向线槽天线的等离子体处理器通过等离子体氮化法形成的氮化硅膜（22）夹在氧化硅膜（21），（23）上的ONO膜之后，位线扩散层（17） ）通过离子注入形成在存储单元阵列区域（11）中，作为抗蚀剂图案（16）作为掩模，然后通过进一步的离子注入向氮化硅膜（22）提供晶格缺陷。 因此，可以实现在低温条件下形成高质量氮化物膜的高度可靠的半导体存储器件，此外，氮化物膜可以用作具有充分适应于 小型化和高度一体化是最近的需求。