公开(公告)号：US06690044B1

公开(公告)日：2004-02-10

申请号：US08859629

申请日：1997-05-20

申请人： Trung T. Doan ,  Randhir P. S. Thakur ,  Yauh-Ching Liu

发明人： Trung T. Doan ,  Randhir P. S. Thakur ,  Yauh-Ching Liu

IPC分类号： H01L2980

CPC分类号： H01L21/321 ,  H01L21/31051

摘要： A multilayer heterostructure is provided a planarization layer superjacent a semiconductor substrate. The planarization layer comprises tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (“BPSG”) or tetraethylorthosilicate (“TEOS”). A barrier film having a structural integrity is superjacent the planarization layer. A second layer is formed superjacent the barrier film. The second layer comprises tungsten, titanium, tantalum, copper, aluminum, borophosphosilicate glass (“BPSG”) or tetraethylorthosilicate (“TEOS”). Heating causes the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step. Further, the planarization layer goes through a solid state reaction and the second layer obtains a uniform reflow.

摘要翻译： 提供了多层异质结构，该平面化层位于半导体衬底的上方。 平坦化层包括钨，钛，钽，铜，铝，单晶硅，多晶硅，非晶硅，硼磷硅酸盐玻璃（“BPSG”）或原硅酸四乙酯（“TEOS”）。 具有结构完整性的阻挡膜位于平坦化层的上方。 在阻挡膜的上方形成第二层。 第二层包括钨，钛，钽，铜，铝，硼磷硅酸玻璃（“BPSG”）或原硅酸四乙酯（“TEOS”）。 加热使得平坦化层根据第一热膨胀系数膨胀，第二层根据第二热膨胀系数膨胀，并且要保持的阻挡膜的结构完整性。 这导致阻挡膜将平坦化层与第二层隔离，从而防止平面化层和第二层在加热步骤期间相互作用。 此外，平坦化层经历固态反应，第二层获得均匀的回流。

公开(公告)号：US5372974A

公开(公告)日：1994-12-13

申请号：US34339

申请日：1993-03-19

申请人： Trung T. Doan ,  Randhir P. S. Thakur ,  Yauh-Ching Liu

发明人： Trung T. Doan ,  Randhir P. S. Thakur ,  Yauh-Ching Liu

IPC分类号： H01L21/3105 ,  H01L21/321 ,  H01L21/02

CPC分类号： H01L21/321 ,  H01L21/31051 ,  Y10S438/938

摘要： A method for reducing the effects of buckling, cracking, or wrinkling in multilayer heterostructures is provided. The method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed superjacent the planarization layer by exposing the substrate to a gas and radiant energy. A second layer is formed superjacent the barrier film. The substrate is heated to cause the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step. Further, it enables the planarization layer to go through a solid state reaction and the second layer to obtain a uniform reflow.

摘要翻译： 提供了减少多层异质结构中的翘曲，开裂或皱纹的影响的方法。 该方法包括在半导体衬底之上形成平坦化层。 具有结构完整性的阻挡膜通过将衬底暴露于气体和辐射能而在平坦化层的上方形成。 在阻挡膜的上方形成第二层。 基板被加热以使平坦化层根据第一热膨胀系数膨胀，第二层根据第二热膨胀系数膨胀，并且要保持的阻挡膜的结构完整性。 这导致阻挡膜将平坦化层与第二层隔离，从而防止平面化层和第二层在加热步骤期间相互作用。 此外，其使得平坦化层能够经历固态反应和第二层以获得均匀的回流。

公开(公告)号：US07485961B2

公开(公告)日：2009-02-03

申请号：US10774762

申请日：2004-02-09

申请人： Trung T. Doan ,  Randhir P. S. Thakur ,  Yauh-Ching Liu

发明人： Trung T. Doan ,  Randhir P. S. Thakur ,  Yauh-Ching Liu

IPC分类号： H01L23/48

CPC分类号： H01L21/321 ,  H01L21/31051

摘要： A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed superjacent the planarization layer. A second layer is formed superjacent the barrier film. The substrate is heated sufficiently to cause the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step.

摘要翻译： 公开了一种减少翘曲效应的方法，也称为多层异质结构中的开裂或起皱。 本方法包括在半导体衬底之上形成平坦化层。 具有结构完整性的阻挡膜形成在平坦化层的上方。 在阻挡膜的上方形成第二层。 将基板充分加热以使平坦化层根据第一热膨胀系数膨胀，第二层根据第二热膨胀系数膨胀，并保持所述阻挡膜的结构完整性。 这导致阻挡膜将平坦化层与第二层隔离，从而防止平面化层和第二层在加热步骤期间相互作用。

公开(公告)号：US06365452B1

公开(公告)日：2002-04-02

申请号：US09724608

申请日：2000-11-28

申请人： Dung-Ching Perng ,  Yauh-Ching Liu

发明人： Dung-Ching Perng ,  Yauh-Ching Liu

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L21/76237 ,  H01L27/1087 ,  H01L28/55 ,  H01L29/66181

摘要： A DRAM cell capacitor and access transistor are described. Capacitor formation, access transistor fabrication and cell isolation methods are integrated by using isolation trench sidewalls to form DRAM capacitors and access transistors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor. A vertically oriented access transistor is formed over top of the capacitor. To accomplish this, an isolation dielectric is deposited and patterned to provide a support structure for gate electrodes of the vertical access transistor above the trench sidewall capacitors. After gate structure formation the support layer is replaced with selectively doped epitaxial silicon in which the transistor's channel, source, and drain are formed.

摘要翻译： 描述了DRAM单元电容器和存取晶体管。 通过使用隔离沟槽侧壁来形成DRAM电容器和存取晶体管来集成电容器形成，存取晶体管制造和电池隔离方法。 与隔离沟槽的垂直侧壁相邻的掺杂硅衬底提供一个DRAM单元电容器板。 DRAM电容器还包含部分地覆盖隔离沟槽的内部垂直侧壁的电介质材料。 覆盖隔离沟槽的垂直侧壁上的介电材料的导电层形成第二电容器板并完成DRAM电容器。 在电容器顶部形成垂直取向的存取晶体管。 为了实现这一点，沉积和图案化隔离电介质以为沟槽侧壁电容器上方的垂直存取晶体管的栅电极提供支撑结构。 在门结构形成之后，通过形成晶体管的沟道，源极和漏极的选择性掺杂的外延硅替代支撑层。

公开(公告)号：US06316312B2

公开(公告)日：2001-11-13

申请号：US09730648

申请日：2000-12-05

申请人： Yauh-Ching Liu ,  David Y. Kao

发明人： Yauh-Ching Liu ,  David Y. Kao

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

摘要： Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer. The invention also includes a construction comprising: a) an opening extending through an insulative layer to a node location; b) a conductive spacer within the opening and narrowing at least a portion of the opening; the conductive spacer having inner and outer surfaces; c) a storage node layer in connecting with the node location and extending along both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; and d) a dielectric layer and a cell plate layer operatively proximate the storage node.

公开(公告)号：US06177699B1

公开(公告)日：2001-01-23

申请号：US09083373

申请日：1998-05-21

申请人： Dung-Ching Perng ,  Yauh-Ching Liu

发明人： Dung-Ching Perng ,  Yauh-Ching Liu

IPC分类号： H01L27108

CPC分类号： H01L27/10861 ,  H01L21/76237 ,  H01L27/1087 ,  H01L28/55 ,  H01L29/66181

摘要： A DRAM cell capacitor and access transistor are described. Capacitor formation, access transistor fabrication and cell isolation methods are integrated by using isolation trench sidewalls to form DRAM capacitors and access transistors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor. A vertically oriented access transistor is formed over top of the capacitor. To accomplish this, an isolation dielectric is deposited and patterned to provide a support structure for gate electrodes of the vertical access transistor above the trench sidewall capacitors. After gate structure formation the support layer is replaced with selectively doped epitaxial silicon in which the transistor's channel, source, and drain are formed.

摘要翻译： 描述了DRAM单元电容器和存取晶体管。 通过使用隔离沟槽侧壁来形成DRAM电容器和存取晶体管来集成电容器形成，存取晶体管制造和电池隔离方法。 与隔离沟槽的垂直侧壁相邻的掺杂硅衬底提供一个DRAM单元电容器板。 DRAM电容器还包含部分地覆盖隔离沟槽的内部垂直侧壁的电介质材料。 覆盖隔离沟槽的垂直侧壁上的介电材料的导电层形成第二电容器板并完成DRAM电容器。 在电容器顶部形成垂直取向的存取晶体管。 为了实现这一点，沉积和图案化隔离电介质以为沟槽侧壁电容器上方的垂直存取晶体管的栅电极提供支撑结构。 在门结构形成之后，通过形成晶体管的沟道，源极和漏极的选择性掺杂的外延硅替代支撑层。

公开(公告)号：US6061264A

公开(公告)日：2000-05-09

申请号：US118602

申请日：1998-07-17

申请人： Gary K. Giust ,  Ruggero Castagnetti ,  Yauh-Ching Liu ,  Subramanian Ramesh

发明人： Gary K. Giust ,  Ruggero Castagnetti ,  Yauh-Ching Liu ,  Subramanian Ramesh

IPC分类号： G11C17/14 ,  G11C11/42 ,  G11C13/04

CPC分类号： G11C17/14

摘要： Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithography and an anti-reflective coating. The self-alignment allows the size and location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication.

摘要翻译： 提供了自对准的半导体熔丝结构，制造这种熔丝结构的方法，以及结合这样的熔丝结构的装置。 保险丝断点，熔断器的电气连接部分被激光束切断的点，通过使用光刻和抗反射涂层进行自对准。 自对准允许断点的尺寸和位置对激光束的尺寸和对准不太敏感。 这具有几个优点，包括允许光刻控制和激光光斑照射熔丝材料和周围结构的有效尺寸减小。 这允许减小熔丝间距，增加密度和使用芯片面积的效率，并且导致减少的热暴露，这对芯片造成较小的损坏。 此外，激光对准不太关键，因此耗时更少，这增加了制造中的吞吐量。

公开(公告)号：US6037233A

公开(公告)日：2000-03-14

申请号：US69027

申请日：1998-04-27

申请人： Yauh-Ching Liu ,  Gary K. Giust ,  Ruggero Castagnetti ,  Subramanian Ramesh

发明人： Yauh-Ching Liu ,  Gary K. Giust ,  Ruggero Castagnetti ,  Subramanian Ramesh

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC分类号： H01L29/66515 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/66575

摘要： Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.

摘要翻译： 提供了在MOS晶体管中的多晶硅栅电极/互连的水平和垂直表面上形成金属层的方法，以及具有金属封装的栅极和互连的器件。 本发明的金属封装方法还可以在晶体管的源极和漏极区域的暴露表面上提供金属层。 本发明的方法和装置允许减少器件电阻和信号传播延迟。

公开(公告)号：US5905280A

公开(公告)日：1999-05-18

申请号：US798241

申请日：1997-02-11

申请人： Yauh-Ching Liu ,  David Y. Kao

发明人： Yauh-Ching Liu ,  David Y. Kao

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L21/76895 ,  H01L28/84 ,  H01L28/90

摘要： The invention includes a construction comprising: a) an opening extending through an insulative layer to a node location; b) a conductive spacer within the opening and narrowing at least a portion of the opening; the conductive spacer having inner and outer surfaces; c) a storage node layer in connecting with the node location and extending along both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; and d) a dielectric layer and a cell plate layer operatively proximate the storage node.

摘要翻译： 本发明包括一种结构，包括：a）延伸穿过绝缘层到达节点位置的开口; b）在开口内的导电间隔件，并使开口的至少一部分变窄; 导电间隔件具有内表面和外表面; c）与所述节点位置连接并沿着所述导电间隔物的内表面和外表面延伸的存储节点层，所述存储节点层和导电间隔物一起形成电容器存储节点; 以及d）可操作地接近存储节点的电介质层和电池板层。

公开(公告)号：US5371701A

公开(公告)日：1994-12-06

申请号：US223477

申请日：1994-04-05

申请人： Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre Fazan ,  Steven D. Cummings

发明人： Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre Fazan ,  Steven D. Cummings

IPC分类号： H01L27/108 ,  H01L29/68

CPC分类号： H01L27/10817

摘要： A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.

摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠三角形电池（SDC）电容器。 SDC由具有倒三角形横截面的多晶硅结构构成，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。 多晶硅结构的添加增加了存储能力120％，而不会扩大为正常层叠电容器单元限定的表面积。