公开(公告)号：US09063098B2

公开(公告)日：2015-06-23

申请号：US13549482

申请日：2012-07-15

申请人： Tsuneo Terasawa ,  Osamu Suga

发明人： Tsuneo Terasawa ,  Osamu Suga

IPC分类号： G03F1/84 ,  G01N21/88 ,  G01N21/956

CPC分类号： G03F1/22 ,  G01N21/8806 ,  G01N21/95 ,  G01N21/956 ,  G01N2021/8822 ,  G01N2021/95676 ,  G01N2201/061 ,  G03F1/84

摘要： There is provided a method of high-sensitively detecting both of a phase defect existing in a mask blank and a phase defect remaining after manufacturing an EUVL mask. When the mask blank is inspected, EUV light having illumination NA to be within an inner NA but a larger value is irradiated. When the EUVL mask is inspected, by using a dark-field imaging optical system including a center shielding portion for shielding EUV light and a linear shielding portion for shielding the EUV light whose width is smaller than a diameter of the center shielding portion, the center shielding portion and the linear shielding portion being included in a pupil plane, the EUV light having illumination NA as large as or smaller than the width of the linear shielding portion is irradiated.

摘要翻译： 提供了一种高灵敏度地检测存在于掩模坯料中的相位缺陷和在制造EUVL掩模之后剩余的相缺陷的方法。 当检查掩模毛坯时，照射具有NA内但NA值越大的EUV光。 当检查EUVL掩模时，通过使用包括用于屏蔽EUV光的中心屏蔽部分和用于屏蔽宽度小于中心屏蔽部分的直径的EUV光的线性屏蔽部分的暗视场成像光学系统，中心 屏蔽部分和线性屏蔽部分包括在光瞳平面中，照射具有大于或等于线状屏蔽部分的宽度的照明NA的EUV光。

公开(公告)号：US08488866B2

公开(公告)日：2013-07-16

申请号：US12708041

申请日：2010-02-18

申请人： Tsuneo Terasawa ,  Toshihiko Tanaka ,  Hiroyuki Shigemura ,  Hajime Aoyama ,  Osamu Suga

发明人： Tsuneo Terasawa ,  Toshihiko Tanaka ,  Hiroyuki Shigemura ,  Hajime Aoyama ,  Osamu Suga

IPC分类号： G06K9/00

CPC分类号： G01N21/9501 ,  B82Y10/00 ,  B82Y40/00 ,  G01N21/956 ,  G03F1/24 ,  G03F1/84 ,  G03F7/70941 ,  G06T7/0006 ,  G06T2207/30148

摘要： A inspection image data of the chip A is captured and the data representing the amount of correction of flare corresponded to the chip A is appropriately loaded from the map storage block. Next, a inspection image of the chip A′ is captured, and the data representing the amount of correction of flare corresponded to the chip A′ is loaded from the flare map storage block as the amount of shifting of the edge of the contour of the pattern. The amount of correction is converted, by a correction data generation block which is a correction data generator, into the amount of geometrical correction of pattern which provides correction data. In the comparison block, the images of the geometry of two chips are compared and corrected on the amount of correction of flare generated by a correction data generation block, to thereby judge whether defect is found or not.

摘要翻译： 捕获芯片A的检查图像数据，并且从地图存储块适当地加载表示对应于芯片A的闪光的校正量的数据。 接下来，捕获芯片A'的检查图像，并且表示与芯片A'相对应的闪光量的校正量的数据从闪光图存储块加载为轮廓的边缘的移位量 模式。 通过作为校正数据生成器的校正数据生成块将修正量转换为提供校正数据的图案的几何校正量。 在比较块中，对由校正数据生成块生成的闪光的校正量进行比较和修正两个芯片的几何图像，从而判断是否存在缺陷。

公开(公告)号：US20070074146A1

公开(公告)日：2007-03-29

申请号：US11526783

申请日：2006-09-26

申请人： Toshihiko Tanaka ,  Osamu Suga ,  Tsuneo Terasawa ,  Tetsuya Higuchi ,  Hidenori Sakanashi ,  Hirokazu Nosato ,  Tetsuaki Matsunawa

发明人： Toshihiko Tanaka ,  Osamu Suga ,  Tsuneo Terasawa ,  Tetsuya Higuchi ,  Hidenori Sakanashi ,  Hirokazu Nosato ,  Tetsuaki Matsunawa

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A semiconductor chip is manufactured using a cell library pattern obtained by performing OPC (optical proximity correction) process at the time of a cell single arrangement to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance. A plurality of cell libraries are arranged to design a mask pattern and a correction amount of OPC performed to the cell libraries is changed with taking into account the influence of a pattern of cell libraries arranged around a target cell. Further, a cell group with the same arrangement of surrounding cells including the target cell is extracted and is registered as a cell set, and a cell set with the same cell arrangement as that of the registered cell set is produced by copying without re-calculating OPC inside the cell set.

摘要翻译： 使用通过在单元格单元配置时对预先形成半导体电路图案的基本结构的单元库图案执行OPC（光学邻近校正）处理而获得的单元库模式来制造半导体芯片。 布置多个单元库以设计掩模图案，并且考虑到布置在目标单元周围的单元库的图案的影响，改变对单元库执行的OPC的校正量。 此外，提取具有包括目标单元的周围单元的相同排列的单元组，并将其注册为单元组，并且通过复制产生具有与注册单元组相同单元布置的单元组，而不重新计算 OPC内部的单元格集。

公开(公告)号：US20130244142A1

公开(公告)日：2013-09-19

申请号：US13840489

申请日：2013-03-15

申请人： KABUSHIKI KAISHA TOSHIBA ,  TSUNEO TERASAWA

发明人： Takeshi YAMANE ,  Tsuneo Terasawa

IPC分类号： G01N21/956 ,  G03F1/00

CPC分类号： G01N21/956 ,  G01N2021/95676 ,  G03F1/00 ,  G03F1/24

摘要： According to one embodiment, a method of inspecting a mask substrate for defects, includes acquiring a defocus image of a partial region of a mask substrate using a dark-field optical system, acquiring a just-focus image of the partial region using the dark-field optical system, generating a set composed of first signals obtained from the defocus image and having signal intensities equal to or higher than a first threshold value, excluding, from the set, the first signals pertaining to parts in which signal intensities of signals obtained from the just-focus image are equal to or higher than a second threshold value, determining an inspection threshold value for signal intensities, on the basis of the first signals not excluded from, and remaining in, the sea.

摘要翻译： 根据一个实施例，一种用于检查掩模基板的缺陷的方法包括使用暗视场光学系统获取掩模基板的部分区域的散焦图像，使用暗视场光学系统获取部分区域的正焦点图像， 产生由散焦图像获得的具有等于或高于第一阈值的信号强度的由第一信号组成的集合，从集合中除去与从第一阈值获得的信号的信号强度相关的部分的第一信号， 正焦点图像等于或高于第二阈值，基于未从集合中排除和保留的第一信号确定信号强度的检查阈值。

公开(公告)号：US08435702B2

公开(公告)日：2013-05-07

申请号：US12563265

申请日：2009-09-21

申请人： Tsuneo Terasawa ,  Takeshi Yamane

发明人： Tsuneo Terasawa ,  Takeshi Yamane

IPC分类号： G03F1/00

CPC分类号： G03F1/24 ,  B82Y10/00 ,  B82Y40/00 ,  Y10T403/13

摘要： Provided is a technique capable of improving the dimensional accuracy of a transfer pattern in a lithography technique in which EUV light is used and the EUV light is incident obliquely on a mask and an image of the EUV light reflected from the mask is formed on a semiconductor substrate (resist film), thereby transferring the pattern formed on the mask onto the semiconductor substrate. The present invention is based on a lithography technique in which EUV light is used and an exposure optical system in which the EUV light is obliquely incident on a mask is used. In this lithography technique, an absorber and a difference in level are formed on the mask, and a projective component projected on a mask surface out of a direction cosine component of the incident light is set to be almost orthogonal to an extending direction of the difference in level.

摘要翻译： 提供了一种技术，其能够提高使用EUV光的光刻技术中的转印图案的尺寸精度，并且EUV光倾斜地入射到掩模上，并且在半导体上形成从掩模反射的EUV光的图像 衬底（抗蚀剂膜），从而将形成在掩模上的图案转印到半导体衬底上。 本发明基于使用EUV光的光刻技术和其中EUV光倾斜入射在掩模上的曝光光学系统。 在该光刻技术中，在掩模上形成吸收体和水平差，并且投射到入射光的方向余弦分量的掩模表面上的投射分量被设定为与差异的延伸方向几乎正交 在水平。

公开(公告)号：US20120224051A1

公开(公告)日：2012-09-06

申请号：US13409846

申请日：2012-03-01

申请人： Takeshi YAMANE ,  Tsuneo Terasawa

发明人： Takeshi YAMANE ,  Tsuneo Terasawa

IPC分类号： H04N7/18

CPC分类号： G03F1/84 ,  G03F1/22

摘要： According to one embodiment, a method of inspecting a defect of a semiconductor exposure mask by using an optical system, which is configured to acquire an image by an imaging module by making light of an arbitrary wavelength incident on the semiconductor exposure mask, includes acquiring a control condition for elongating a point image acquired by the optical system in a read-out direction of the imaging module, acquiring an image of a desired area of the mask under the control condition, and determining, when a peak signal with a signal intensity which is a first threshold or more.

摘要翻译： 根据一个实施例，通过使用被配置为通过使入射在半导体曝光掩模上的任意波长的光获取成像模块的图像的光学系统来检查半导体曝光掩模的缺陷的方法包括： 控制条件，用于在所述摄像模块的读出方向上延伸由所述光学系统获取的点图像，在所述控制条件下获取所述掩模的期望区域的图像，以及当将具有信号强度的峰值信号 是第一个门槛以上。

公开(公告)号：US20120218543A1

公开(公告)日：2012-08-30

申请号：US13403105

申请日：2012-02-23

申请人： Takeshi YAMANE ,  Tsuneo Terasawa

发明人： Takeshi YAMANE ,  Tsuneo Terasawa

IPC分类号： G01J3/00 ,  G01N21/00

CPC分类号： G01N21/956 ,  G01N2021/8822 ,  G01N2021/95676

摘要： According to one embodiment, a method of detecting a defect of a semiconductor exposure mask includes acquiring a background intensity from a surface height distribution of the mask, acquiring a standard background intensity distribution from the background intensity, making light of an arbitrary wavelength incident on the mask, and acquiring an image at a position of interest of the mask, acquiring background intensity raw data, based on a signal intensity of the acquired image at the position of interest and a mean value of image intensity data in a peripheral area of the position of interest, finding a correction coefficient of the signal intensity, based on a ratio of the background intensity raw data to the standard background intensity distribution, correcting the signal intensity by multiplying the signal intensity.

摘要翻译： 根据一个实施例，一种检测半导体曝光掩模的缺陷的方法包括从掩模的表面高度分布获取背景强度，从背景强度获取标准背景强度分布，使入射到 掩模，并且获取所述掩模的感兴趣位置处的图像，基于感兴趣位置处获取的图像的信号强度和所述位置的周边区域中的图像强度数据的平均值来获取背景强度原始数据 根据背景强度原始数据与标准背景强度分布的比率，求出信号强度的校正系数，通过乘以信号强度来校正信号强度。

公开(公告)号：US07361530B2

公开(公告)日：2008-04-22

申请号：US11714837

申请日：2007-03-07

申请人： Tsuneo Terasawa ,  Toshihiko Tanaka ,  Ko Miyazaki ,  Norio Hasegawa ,  Kazutaka Mori

发明人： Tsuneo Terasawa ,  Toshihiko Tanaka ,  Ko Miyazaki ,  Norio Hasegawa ,  Kazutaka Mori

IPC分类号： H01L21/58

CPC分类号： G03F7/70425 ,  G03F1/00 ,  G03F1/56 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15311 ,  Y10S438/944 ,  Y10S438/946 ,  H01L2924/00

摘要： Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.

摘要翻译： 提高了半导体集成电路器件的生产率。 根据使用光掩模的次数，适当地使用具有由金属制成的不透明图案的光掩模和由抗蚀剂膜制成的不透明图案的光掩模，从而进行曝光处理。

公开(公告)号：US06849540B2

公开(公告)日：2005-02-01

申请号：US10296495

申请日：2001-08-15

申请人： Tsuneo Terasawa ,  Toshihiko Tanaka ,  Ko Miyazaki ,  Norio Hasegawa ,  Kazutaka Mori

发明人： Tsuneo Terasawa ,  Toshihiko Tanaka ,  Ko Miyazaki ,  Norio Hasegawa ,  Kazutaka Mori

IPC分类号： G03F1/54 ,  G03F1/56 ,  G03F7/20 ,  H01L21/768 ,  H01L21/027

CPC分类号： G03F7/70425 ,  G03F1/00 ,  G03F1/56 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15311 ,  Y10S438/944 ,  Y10S438/946 ,  H01L2924/00

摘要： Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.

摘要翻译： 提高了半导体集成电路器件的生产率。 根据使用光掩模的次数，适当地使用具有由金属制成的不透明图案的光掩模和由抗蚀剂膜制成的不透明图案的光掩模，从而进行曝光处理。

公开(公告)号：US06677107B1

公开(公告)日：2004-01-13

申请号：US09646036

申请日：2000-09-13

申请人： Norio Hasegawa ,  Tsuneo Terasawa ,  Toshihiko Tanaka

发明人： Norio Hasegawa ,  Tsuneo Terasawa ,  Toshihiko Tanaka

IPC分类号： G03C500

CPC分类号： G03F1/56 ,  G03F1/44 ,  G03F1/62 ,  G03F7/70983

摘要： In order to suppress or prevent the occurrence of foreign matter in the manufacture of a semiconductor integrated circuit device by the use of a photo mask constituted in such a manner that a resist film is made to function as a light screening film, inspection or exposure treatment is carried out, when the photo mask 1PA1 has been mounted on a predetermined apparatus such as, e.g., an inspection equipment or aligner, in the state in which a mounting portion 2 of the predetermined apparatus is contacted with that region of a major surface of a mask substrate 1a of the photo mask 1PA1 in which a light shielding pattern 1b and a mask pattern 1mr, each formed of a resist film, on the major surface of the mask substrate 1a do not exist.

摘要翻译： 为了通过使用以使抗蚀剂膜作为遮光膜的方式构成的光掩模来抑制或防止在制造半导体集成电路器件时发生异物，检查或曝光处理 当在预定设备的安装部分2与主要表面的区域接触的状态下，当光掩模1PA1已经安装在诸如检查设备或对准器的预定设备上时， 在掩模基板1a的主表面上不存在其中由抗蚀剂膜形成的遮光图案1b和掩模图案1mr的光掩模1PA1的掩模基板1a。