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    Method for designing mask pattern and method for manufacturing semiconductor device
    1.
    发明申请
    Method for designing mask pattern and method for manufacturing semiconductor device 审中-公开
    设计掩模图案的方法和制造半导体器件的方法

    公开(公告)号：US20070074146A1

    公开(公告)日：2007-03-29

    申请号：US11526783

    申请日：2006-09-26

    申请人： Toshihiko Tanaka ,  Osamu Suga ,  Tsuneo Terasawa ,  Tetsuya Higuchi ,  Hidenori Sakanashi ,  Hirokazu Nosato ,  Tetsuaki Matsunawa

    发明人： Toshihiko Tanaka ,  Osamu Suga ,  Tsuneo Terasawa ,  Tetsuya Higuchi ,  Hidenori Sakanashi ,  Hirokazu Nosato ,  Tetsuaki Matsunawa

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A semiconductor chip is manufactured using a cell library pattern obtained by performing OPC (optical proximity correction) process at the time of a cell single arrangement to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance. A plurality of cell libraries are arranged to design a mask pattern and a correction amount of OPC performed to the cell libraries is changed with taking into account the influence of a pattern of cell libraries arranged around a target cell. Further, a cell group with the same arrangement of surrounding cells including the target cell is extracted and is registered as a cell set, and a cell set with the same cell arrangement as that of the registered cell set is produced by copying without re-calculating OPC inside the cell set.

    摘要翻译： 使用通过在单元格单元配置时对预先形成半导体电路图案的基本结构的单元库图案执行OPC（光学邻近校正）处理而获得的单元库模式来制造半导体芯片。 布置多个单元库以设计掩模图案，并且考虑到布置在目标单元周围的单元库的图案的影响，改变对单元库执行的OPC的校正量。 此外，提取具有包括目标单元的周围单元的相同排列的单元组，并将其注册为单元组，并且通过复制产生具有与注册单元组相同单元布置的单元组，而不重新计算 OPC内部的单元格集。

    Method for designing mask pattern and method for manufacturing semiconductor device
    2.
    发明申请
    Method for designing mask pattern and method for manufacturing semiconductor device 审中-公开
    设计掩模图案的方法和制造半导体器件的方法

    公开(公告)号：US20080250383A1

    公开(公告)日：2008-10-09

    申请号：US11526820

    申请日：2006-09-26

    申请人： Toshihiko Tanaka ,  Tsuneo Terasawa ,  Nobuyuki Yoshioka ,  Tetsuya Higuchi ,  Hidenori Sakanashi ,  Hirokazu Nosato ,  Masahiro Murakawa

    发明人： Toshihiko Tanaka ,  Tsuneo Terasawa ,  Nobuyuki Yoshioka ,  Tetsuya Higuchi ,  Hidenori Sakanashi ,  Hirokazu Nosato ,  Masahiro Murakawa

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G03F1/36 ,  G06F2217/08

    摘要： A mask pattern designing method capable of achieving the reduction in the increasing OPC processing time, shortening the manufacture TAT of a semiconductor device, and achieving the cost reduction is provided. An OPC (optical proximity correction) process at the time when a cell is singularly arranged is performed to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance, and a semiconductor chip is produced using the cell library pattern to which the OPC process has been performed. At this time, since the cell library pattern which has been OPC-processed in advance is influenced by the cell library patterns around it, the correction process thereof is performed to the end portions of the patterns near the cell boundary. As particularly effective OPC correction means, the genetic algorithm is used.

    摘要翻译： 提供了能够实现OPC处理时间的增加减少，缩短半导体器件的制造TAT以及实现成本降低的掩模图案设计方法。 对单元格单独排列时的OPC（光学邻近校正）处理进行预先对形成半导体电路图案的基本结构的单元库模式，并使用单元库模式生成半导体芯片， 已经执行了OPC过程。 此时，由于预先对其进行了OPC处理的单元库模式受其周围的单元库模式的影响，所以对单元边界附近的图案的端部进行修正处理。 作为特别有效的OPC校正手段，使用遗传算法。

    Mask Pattern Designing Method Using Optical Proximity Correction in Optical Lithography, Designing Device, and Semiconductor Device Manufacturing Method Using the Same
    3.
    发明申请
    Mask Pattern Designing Method Using Optical Proximity Correction in Optical Lithography, Designing Device, and Semiconductor Device Manufacturing Method Using the Same 审中-公开
    光学平版印刷中的光学接近校正的掩模图案设计方法，设计装置和使用其的半导体器件制造方法

    公开(公告)号：US20080276215A1

    公开(公告)日：2008-11-06

    申请号：US11910049

    申请日：2006-03-28

    申请人： Tetsuya Higuchi ,  Hirokazu Nosato ,  Masahiro Murakawa ,  Hidenori Sakanashi ,  Nobuyuki Yoshioka ,  Tsuneo Terasawa ,  Toshihiko Tanaka

    发明人： Tetsuya Higuchi ,  Hirokazu Nosato ,  Masahiro Murakawa ,  Hidenori Sakanashi ,  Nobuyuki Yoshioka ,  Tsuneo Terasawa ,  Toshihiko Tanaka

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0207 ,  G03F1/36 ,  G06N3/126

    摘要： A method for designing a mask pattern realizes shortening the ever-growing time for the OPC treatment, decreases the fabrication TAT of a semiconductor device and cuts cost. A method for fabricating a semiconductor device uses the mask pattern designed. This invention performs the OPC treatment in advance on a cell library constituting the basic configuration of a semiconductor circuit pattern and prepares a semiconductor chip using the cell library that has undergone the OPC treatment. The method for designing a mask pattern includes the steps of designing a cell library pattern by executing for each of the cell libraries a treatment for correcting proximity effect directed to correcting the change of shape taking place during the formation of a pattern by the exposure of a mask pattern, designing a mask pattern by laying out the cell libraries and changing the amount of correction of proximity effect applied to the cell libraries in consideration of the influence of the cell library patterns disposed peripherally. This treatment for correction is executed by the degree of influence exerted by surrounding patterns collected in advance and the genetic algorithm.

    摘要翻译： 用于设计掩模图案的方法实现缩短OPC处理的不断增长的时间，减少半导体器件的制造TAT并降低成本。 半导体器件的制造方法使用设计的掩模图案。 本发明预先在构成半导体电路图案的基本结构的单元库中进行OPC处理，并且使用已经经过OPC处理的单元库来制备半导体芯片。 用于设计掩模图案的方法包括以下步骤：通过针对每个单元库执行用于修正邻近效应的处理的设计单元库模式的步骤，所述处理用于校正在形成模式期间发生的形状变化 掩模图案，考虑到周边设置的细胞库图案的影响，通过铺设细胞库并改变施加到细胞库的邻近效应的校正量来设计掩模图案。 这种校正处理是通过预先收集的周围图案和遗传算法的影响程度来执行的。

    Method of inspecting mask pattern and mask pattern inspection apparatus
    4.
    发明授权
    Method of inspecting mask pattern and mask pattern inspection apparatus 有权
    检查掩模图案和掩模图案检查装置的方法

    公开(公告)号：US08488866B2

    公开(公告)日：2013-07-16

    申请号：US12708041

    申请日：2010-02-18

    申请人： Tsuneo Terasawa ,  Toshihiko Tanaka ,  Hiroyuki Shigemura ,  Hajime Aoyama ,  Osamu Suga

    发明人： Tsuneo Terasawa ,  Toshihiko Tanaka ,  Hiroyuki Shigemura ,  Hajime Aoyama ,  Osamu Suga

    IPC分类号： G06K9/00

    CPC分类号： G01N21/9501 ,  B82Y10/00 ,  B82Y40/00 ,  G01N21/956 ,  G03F1/24 ,  G03F1/84 ,  G03F7/70941 ,  G06T7/0006 ,  G06T2207/30148

    摘要： A inspection image data of the chip A is captured and the data representing the amount of correction of flare corresponded to the chip A is appropriately loaded from the map storage block. Next, a inspection image of the chip A′ is captured, and the data representing the amount of correction of flare corresponded to the chip A′ is loaded from the flare map storage block as the amount of shifting of the edge of the contour of the pattern. The amount of correction is converted, by a correction data generation block which is a correction data generator, into the amount of geometrical correction of pattern which provides correction data. In the comparison block, the images of the geometry of two chips are compared and corrected on the amount of correction of flare generated by a correction data generation block, to thereby judge whether defect is found or not.

    摘要翻译： 捕获芯片A的检查图像数据，并且从地图存储块适当地加载表示对应于芯片A的闪光的校正量的数据。 接下来，捕获芯片A'的检查图像，并且表示与芯片A'相对应的闪光量的校正量的数据从闪光图存储块加载为轮廓的边缘的移位量 模式。 通过作为校正数据生成器的校正数据生成块将修正量转换为提供校正数据的图案的几何校正量。 在比较块中，对由校正数据生成块生成的闪光的校正量进行比较和修正两个芯片的几何图像，从而判断是否存在缺陷。

    Method for manufacturing semiconductor integrated circuit device, optical mask used therefor, method for manufacturing the same, and mask blanks used therefor
    7.
    发明授权
    Method for manufacturing semiconductor integrated circuit device, optical mask used therefor, method for manufacturing the same, and mask blanks used therefor 有权
    用于制造半导体集成电路器件的方法，用于其的光学掩模，其制造方法和用于其的掩模毛坯

    公开(公告)号：US06677107B1

    公开(公告)日：2004-01-13

    申请号：US09646036

    申请日：2000-09-13

    申请人： Norio Hasegawa ,  Tsuneo Terasawa ,  Toshihiko Tanaka

    发明人： Norio Hasegawa ,  Tsuneo Terasawa ,  Toshihiko Tanaka

    IPC分类号： G03C500

    CPC分类号： G03F1/56 ,  G03F1/44 ,  G03F1/62 ,  G03F7/70983

    摘要： In order to suppress or prevent the occurrence of foreign matter in the manufacture of a semiconductor integrated circuit device by the use of a photo mask constituted in such a manner that a resist film is made to function as a light screening film, inspection or exposure treatment is carried out, when the photo mask 1PA1 has been mounted on a predetermined apparatus such as, e.g., an inspection equipment or aligner, in the state in which a mounting portion 2 of the predetermined apparatus is contacted with that region of a major surface of a mask substrate 1a of the photo mask 1PA1 in which a light shielding pattern 1b and a mask pattern 1mr, each formed of a resist film, on the major surface of the mask substrate 1a do not exist.

    摘要翻译： 为了通过使用以使抗蚀剂膜作为遮光膜的方式构成的光掩模来抑制或防止在制造半导体集成电路器件时发生异物，检查或曝光处理 当在预定设备的安装部分2与主要表面的区域接触的状态下，当光掩模1PA1已经安装在诸如检查设备或对准器的预定设备上时， 在掩模基板1a的主表面上不存在其中由抗蚀剂膜形成的遮光图案1b和掩模图案1mr的光掩模1PA1的掩模基板1a。

    MASK DEFECT MEASUREMENT METHOD, MASK QUALITY DETERMINATION METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    10.
    发明申请
    MASK DEFECT MEASUREMENT METHOD, MASK QUALITY DETERMINATION METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    掩模缺陷测量方法，掩模质量测定方法和半导体器件的制造方法

    公开(公告)号：US20110043811A1

    公开(公告)日：2011-02-24

    申请号：US12750396

    申请日：2010-03-30

    申请人： Takeshi Yamane ,  Tsuneo Terasawa ,  Toshihiko Tanaka

    发明人： Takeshi Yamane ,  Tsuneo Terasawa ,  Toshihiko Tanaka

    IPC分类号： G01N21/47 ,  G01N21/00

    CPC分类号： G01N21/956 ,  G01N2021/8874 ,  G01N2021/95676 ,  G03F1/84

    摘要： A method for measuring a shape of a phase defect existing on an exposure mask includes making inspection light incident on the mask, measuring the intensity of light scattered in an angular range in which the width of an scattering area on the phase defect can be predicted, calculating a radius of the phase defect based on the measured scattered light intensity, changing the angular range of scattered light to be measured, remeasuring scattered light intensity in the thus changed angular range, and calculating a scattering cross-sectional area based on the scattered light intensity obtained by remeasurement. A process of remeasuring the scattered light intensity and calculating the scattering cross-sectional area is repeatedly performed until the remeasured scattered light intensity is saturated and the shape of the phase defect is determined by using the calculated radius of the phase defect and each of the calculated scattering cross-sectional areas.

    摘要翻译： 用于测量存在于曝光掩模上的相位缺陷的形状的方法包括：使检测光入射到掩模上，测量在可预测相位缺陷上的散射面积的宽度的角度范围内散射的光的强度， 基于所测量的散射光强度，改变要测量的散射光的角度范围来计算相位缺陷的半径，在如此改变的角度范围内重新测量散射光强度，以及基于散射光计算散射截面积 通过重新测量获得的强度。 重新进行重新测量散射光强度并计算散射横截面积的过程，直到重新测量的散射光强度饱和，并且通过使用计算出的相位缺陷的半径来确定相位缺陷的形状， 散射横截面积。