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公开(公告)号：US20070155052A1
公开(公告)日：2007-07-05
申请号：US11714837
申请日：2007-03-07
Applicant: Tsuneo Terasawa , Toshihiko Tanaka , Ko Miyazaki , Norio Hasegawa , Kazutaka Mori
Inventor： Tsuneo Terasawa , Toshihiko Tanaka , Ko Miyazaki , Norio Hasegawa , Kazutaka Mori
IPC: H01L21/58
CPC classification number: G03F7/70425 , G03F1/00 , G03F1/56 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05569 , H01L2224/05572 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/15311 , Y10S438/944 , Y10S438/946 , H01L2924/00
Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.
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公开(公告)号：US06936406B2
公开(公告)日：2005-08-30
申请号：US10364702
申请日：2003-02-12
Applicant: Norio Hasegawa , Joji Okada , Toshihiko Tanaka , Kazutaka Mori , Ko Miyazaki
Inventor： Norio Hasegawa , Joji Okada , Toshihiko Tanaka , Kazutaka Mori , Ko Miyazaki
CPC classification number: G03F1/56 , G03F1/70 , G03F7/0035 , G03F7/70433 , G03F7/707 , H01L21/0274 , Y10S438/942 , Y10S438/945 , Y10S438/948 , Y10S438/95
Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.
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3.发明授权公开(公告)号：US06622292B2
公开(公告)日：2003-09-16
申请号：US09921794
申请日：2001-08-06
Applicant: Ko Miyazaki , Kazuhiko Eguchi , Tadaaki Tanimoto
Inventor： Ko Miyazaki , Kazuhiko Eguchi , Tadaaki Tanimoto
IPC: G06F1750
CPC classification number: G06F17/5045
Abstract: The optimization algorithm candidate of a plurality of circuit blocks given with the logic circuit description based on the hardware description language is determined considering the Hamming distance of circuit block (S1 to S3). The common circuit blocks of the optimization algorithm candidate determined in the first process are then grouped considering the coupling degree among circuit blocks (S4 to S6). Result of grouping is the result for the circuit blocks having apparent characteristic in the algorithm candidate and coupling degree and the circuit blocks having uncertain characteristics are also left. In view of optimizing the grouping for the circuit blocks having uncertain characteristics, the grouping of a plurality of circuit blocks is optimized with the hereditary algorithm by reflecting the result of grouping on the initial condition. Thereby, the logical composition for the logic circuit description based on the hardware description language can be optimized and the necessary time can be shortened.
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4.发明授权Method of fabricating a semiconductor integrated circuit that includes patterning a semiconductor substrate with a first photomask that uses metal for blocking light and patterning the same substrate with a second photomask that uses organic resin for blocking light 有权一种半导体集成电路的制造方法，其包括使用第一光掩模图案化半导体衬底，所述第一光掩模使用金属来阻挡光，并且利用使用有机树脂阻挡光的第二光掩模对相同衬底进行图案化公开(公告)号：US07361530B2
公开(公告)日：2008-04-22
申请号：US11714837
申请日：2007-03-07
Applicant: Tsuneo Terasawa , Toshihiko Tanaka , Ko Miyazaki , Norio Hasegawa , Kazutaka Mori
Inventor： Tsuneo Terasawa , Toshihiko Tanaka , Ko Miyazaki , Norio Hasegawa , Kazutaka Mori
IPC: H01L21/58
CPC classification number: G03F7/70425 , G03F1/00 , G03F1/56 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05569 , H01L2224/05572 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/15311 , Y10S438/944 , Y10S438/946 , H01L2924/00
Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.
Abstract translation: 提高了半导体集成电路器件的生产率。 根据使用光掩模的次数，适当地使用具有由金属制成的不透明图案的光掩模和由抗蚀剂膜制成的不透明图案的光掩模，从而进行曝光处理。
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5.发明授权METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF PRODUCING A MULTI-CHIP MODULE THAT INCLUDES PATTERNING WITH A PHOTOMASK THAT USES METAL FOR BLOCKING EXPOSURE LIGHT AND A PHOTOMASK THAT USES ORGANIC RESIN FOR BLOCKING EXPOSURE LIGHT 失效制造半导体集成电路装置的方法以及制造多芯片模块的方法，其包括使用用于阻挡接触光的金属的光电图案，以及使用有机树脂阻挡接触光的照相机公开(公告)号：US06849540B2
公开(公告)日：2005-02-01
申请号：US10296495
申请日：2001-08-15
Applicant: Tsuneo Terasawa , Toshihiko Tanaka , Ko Miyazaki , Norio Hasegawa , Kazutaka Mori
Inventor： Tsuneo Terasawa , Toshihiko Tanaka , Ko Miyazaki , Norio Hasegawa , Kazutaka Mori
IPC: G03F1/54 , G03F1/56 , G03F7/20 , H01L21/768 , H01L21/027
CPC classification number: G03F7/70425 , G03F1/00 , G03F1/56 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05569 , H01L2224/05572 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/15311 , Y10S438/944 , Y10S438/946 , H01L2924/00
Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.
Abstract translation: 提高了半导体集成电路器件的生产率。 根据使用光掩模的次数，适当地使用具有由金属制成的不透明图案的光掩模和由抗蚀剂膜制成的不透明图案的光掩模，从而进行曝光处理。
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Patent Agency Ranking
公开(公告)号：US06846598B2
公开(公告)日：2005-01-25
申请号：US10686723
申请日：2003-10-17
Applicant: Norio Hasegawa , Toshihiko Tanaka , Joji Okada , Kazutaka Mori , Ko Miyazaki
Inventor： Norio Hasegawa , Toshihiko Tanaka , Joji Okada , Kazutaka Mori , Ko Miyazaki
IPC: G03F1/32 , G03F1/38 , G03F1/40 , G03F1/54 , G03F1/56 , G03F1/62 , G03F1/68 , G03F1/80 , G03F7/00 , H01L21/027 , G03F9/00
CPC classification number: G03F1/56 , G03F7/0035
Abstract: In order to shorten the time required to change or correct a mask pattern over a mask, light-shielding patterns formed of a resist film for integrated circuit pattern transfer are partly provided over a mask substrate constituting a photomask in addition to light-shielding patterns formed of a metal for the integrated circuit pattern transfer.
Abstract translation: 为了缩短在掩模上改变或校正掩模图案所需的时间，除了形成的遮光图案之外，在构成光掩模的掩模基板上部分地设置由用于集成电路图案转印的抗蚀剂膜形成的遮光图案 的金属用于集成电路图案转移。
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公开(公告)号：US06656644B2
公开(公告)日：2003-12-02
申请号：US09881701
申请日：2001-06-18
Applicant: Norio Hasegawa , Toshihiko Tanaka , Joji Okada , Kazutaka Mori , Ko Miyazaki
Inventor： Norio Hasegawa , Toshihiko Tanaka , Joji Okada , Kazutaka Mori , Ko Miyazaki
IPC: G03F900
CPC classification number: G03F1/56 , G03F7/0035
Abstract: In order to shorten the time required to change or correct a mask pattern over a mask, light-shielding patterns formed of a resist film for integrated circuit pattern transfer are partly provided over a mask substrate constituting a photomask in addition to light-shielding patterns formed of a metal for the integrated circuit pattern transfer.
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8.发明授权Manufacturing use of photomasks with an opaque pattern comprising an organic layer photoabsorptive to exposure light with wavelengths exceeding 200 NM 失效制造使用具有不透明图案的光掩模，所述不透明图案包括对波长超过200nm的曝光光吸收的有机层公开(公告)号：US06596656B2
公开(公告)日：2003-07-22
申请号：US09931938
申请日：2001-08-20
Applicant: Toshihiko Tanaka , Norio Hasegawa , Kazutaka Mori , Ko Miyazaki , Tsuneo Terasawa
Inventor： Toshihiko Tanaka , Norio Hasegawa , Kazutaka Mori , Ko Miyazaki , Tsuneo Terasawa
IPC: H01L2131
CPC classification number: G03F1/56 , G03F1/00 , G03F1/58 , G03F7/0035 , Y10S438/945
Abstract: A method is provided for well printing a specified pattern even when the exposure treatment using a resist mask uses exposure light with a wavelength over 200 nm. When exposure treatment is applied to a semiconductor wafer by using exposure light with a wavelength over 200 nm, a photomask is used. The photomask is provided with an opaque pattern of a resist layer on an organic layer which is photoabsorptive in reaction to exposure light.
Abstract translation: 即使当使用抗蚀剂掩模的曝光处理使用具有超过200nm的波长的曝光光时，也提供了用于良好地打印指定图案的方法。 当通过使用波长超过200nm的曝光光对半导体晶片进行曝光处理时，使用光掩模。 光掩模在有机层上设置有抗光蚀刻层的不透明图案，其与曝光光反应是光吸收性的。
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公开(公告)号：US5159664A
公开(公告)日：1992-10-27
申请号：US671652
申请日：1991-03-19
Applicant: Tetsuya Yamamoto , Goro Suzuki , Susumu Sugawara , Nobuhiro Hamada , Ko Miyazaki , Tsuyoshi Takahashi , Susumu Tamura , Mikihiko Motoki
Inventor： Tetsuya Yamamoto , Goro Suzuki , Susumu Sugawara , Nobuhiro Hamada , Ko Miyazaki , Tsuyoshi Takahashi , Susumu Tamura , Mikihiko Motoki
CPC classification number: G06F3/0481 , G06F3/04845
Abstract: A graphic processor comprises an input device for inputting a command from an operator, a display device for displaying graphic data and a computer for preparing and correcting graphic data by a command input from the operator and for making display control of the display device. When the operator wants to know the content of the command that is executed, he instructs the command to the computer. A command name, a processing content and a figure as an object of processing are calculated from history data instructed from the computer. The figure as the object of processing, the command processing content and the relation of correspondence are symbolized and displayed on the display device. Furthermore, a parametric figure is also displayed visually on the display device.
Abstract translation: 图形处理器包括用于输入来自操作者的命令的输入装置，用于显示图形数据的显示装置和用于通过从操作者输入的命令来准备和校正图形数据的计算机，并且用于进行显示装置的显示控制。 当操作员想知道所执行的命令的内容时，他向计算机指示命令。 根据从计算机指示的历史数据计算作为处理对象的命令名称，处理内容和图形。 作为处理对象的图形，命令处理内容和对应关系被符号化并显示在显示装置上。 此外，在显示装置上也可视地显示参数图。
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公开(公告)号：US06902868B2
公开(公告)日：2005-06-07
申请号：US10311456
申请日：2001-06-28
Applicant: Norio Hasegawa , Joji Okada , Toshihiko Tanaka , Kazutaka Mori , Ko Miyazaki
Inventor： Norio Hasegawa , Joji Okada , Toshihiko Tanaka , Kazutaka Mori , Ko Miyazaki
CPC classification number: G03F1/56 , G03F1/70 , G03F7/0035 , G03F7/70433 , G03F7/707 , H01L21/0274 , Y10S438/942 , Y10S438/945 , Y10S438/948 , Y10S438/95
Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with a light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.
Abstract translation: 为了缩短开发和制造半导体集成电路器件的周期，在通过曝光处理将集成电路图案转印到晶片上时，使用光掩模PM 1，其部分地设置有遮光图案3 除了由金属形成的遮光图案之外还形成有抗蚀剂膜。
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