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    Method for manufacturing silicon carbide substrate
    3.
    发明授权
    Method for manufacturing silicon carbide substrate 失效
    碳化硅基板的制造方法

    公开(公告)号：US08435866B2

    公开(公告)日：2013-05-07

    申请号：US13256991

    申请日：2010-09-28

    申请人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

    发明人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

    IPC分类号： H01L21/306 ,  H01L21/304

    CPC分类号： C30B29/36 ,  C30B33/06

    摘要： At least one single crystal substrate, each having a backside surface and made of silicon carbide, and a supporting portion having a main surface and made of silicon carbide, are prepared. In this preparing step, at least one of the backside surface and main surface is formed by machining. By this forming step, a surface layer having distortion in the crystal structure is formed on at least one of the backside surface and main surface. The surface layer is removed at least partially. Following this removing step, the backside surface and main surface are connected to each other.

    摘要翻译： 制备至少一个具有背面并由碳化硅制成的单晶基板和具有主表面并由碳化硅制成的支撑部分。 在该制备步骤中，通过机械加工形成背面和主表面中的至少一个。 通过该形成步骤，在背面和主面中的至少一个上形成有晶体结构变形的表层。 表面层至少部分去除。 在该去除步骤之后，背面和主表面彼此连接。

    METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE
    8.
    发明申请
    METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE 失效
    制造碳化硅基板的方法

    公开(公告)号：US20120009761A1

    公开(公告)日：2012-01-12

    申请号：US13256991

    申请日：2010-09-28

    申请人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

    发明人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

    IPC分类号： H01L21/306 ,  H01L21/304

    CPC分类号： C30B29/36 ,  C30B33/06

    摘要： At least one single crystal substrate, each having a backside surface and made of silicon carbide, and a supporting portion having a main surface and made of silicon carbide, are prepared. In this preparing step, at least one of the backside surface and main surface is formed by machining. By this forming step, a surface layer having distortion in the crystal structure is formed on at least one of the backside surface and main surface. The surface layer is removed at least partially. Following this removing step, the backside surface and main surface are connected to each other.

    摘要翻译： 制备至少一个具有背面并由碳化硅制成的单晶基板和具有主表面并由碳化硅制成的支撑部分。 在该制备步骤中，通过机械加工形成背面和主表面中的至少一个。 通过该形成步骤，在背面和主面中的至少一个上形成有晶体结构变形的表层。 表面层至少部分去除。 在该去除步骤之后，背面和主表面彼此连接。

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20120056202A1

    公开(公告)日：2012-03-08

    申请号：US13320247

    申请日：2010-04-27

    申请人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga ,  Makoto Sasaki ,  Taro Nishiguchi ,  Yasuo Namikawa ,  Shinsuke Fujiwara

    发明人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga ,  Makoto Sasaki ,  Taro Nishiguchi ,  Yasuo Namikawa ,  Shinsuke Fujiwara

    IPC分类号： H01L29/24

    CPC分类号： H01L29/7802 ,  C30B23/00 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

    摘要： A MOSFET, which is a semiconductor device allowing for reduced on-resistance while restraining stacking faults from being produced due to heat treatment in a device manufacturing process, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source contact electrode disposed on the active layer; and a drain electrode formed on the other main surface of the silicon carbide substrate. The silicon carbide substrate includes: a base layer made of silicon carbide; and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. Further, the base layer has an impurity concentration greater than 2×1019 cm−3, and the SiC layer has an impurity concentration greater than 5×1018 cm−3 and smaller than 2×1019 cm−3.

    摘要翻译： 一种MOSFET，其是在器件制造工艺中由于热处理而允许抑制堆垛层错而产生降低的导通电阻的半导体器件，包括：碳化硅衬底; 由单晶碳化硅构成的有源层，设置在碳化硅基板的一个主面上; 设置在有源层上的源极接触电极; 以及形成在碳化硅衬底的另一个主表面上的漏电极。 碳化硅基板包括：由碳化硅制成的基层; 以及由单晶碳化硅制成并设置在基底层上的SiC层。 此外，基底层的杂质浓度大于2×1019cm-3，并且SiC层的杂质浓度大于5×1018cm-3且小于2×1019cm-3。