公开(公告)号：US20070164342A1

公开(公告)日：2007-07-19

申请号：US11651965

申请日：2007-01-11

申请人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada ,  Masamichi Matsuoka

发明人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada ,  Masamichi Matsuoka

IPC分类号： H01L29/76

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： A polysilicon film forming a memory gate interconnection and the like includes a part extending from a part positioned on one side surface of a control gate interconnection to a side opposite to a side where the control gate interconnection is positioned, and that part serves as a pad portion. A contact hole is formed to expose the pad portion. The height of a part of the polysilicon film that is positioned on one side surface of the control gate interconnection is set equal to or lower than the height of the control gate interconnection so that the polysilicon film forming a memory gate interconnection and the like does not two-dimensionally overlap the control gate interconnection. Therefore, a semiconductor memory device with increased process margin can be obtained.

摘要翻译： 形成存储器栅互连等的多晶硅膜包括从位于控制栅互连的一个侧表面上的部分延伸到与控制栅互连的一侧相对的一侧的部分，并且该部分用作焊盘 一部分。 形成接触孔以露出焊盘部分。 位于控制栅极互连的一个侧面上的多晶硅膜的一部分的高度设定为等于或低于控制栅极互连的高度，使得形成存储器栅互连等的多晶硅膜不会 二维重叠控制门互连。 因此，可以获得具有增加的工艺裕量的半导体存储器件。

公开(公告)号：US07816207B2

公开(公告)日：2010-10-19

申请号：US12719524

申请日：2010-03-08

申请人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

发明人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

公开(公告)号：US07709874B2

公开(公告)日：2010-05-04

申请号：US11649208

申请日：2007-01-04

申请人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

发明人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

IPC分类号： H01L29/94

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

公开(公告)号：US07939448B2

公开(公告)日：2011-05-10

申请号：US12888995

申请日：2010-09-23

申请人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

发明人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

IPC分类号： H01L21/311

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

公开(公告)号：US20110014783A1

公开(公告)日：2011-01-20

申请号：US12888995

申请日：2010-09-23

申请人： Tsutomu OKAZAKI ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

发明人： Tsutomu OKAZAKI ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

IPC分类号： H01L21/283

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

公开(公告)号：US20100159687A1

公开(公告)日：2010-06-24

申请号：US12719524

申请日：2010-03-08

申请人： Tsutomu OKAZAKI ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

发明人： Tsutomu OKAZAKI ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

IPC分类号： H01L21/28

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

公开(公告)号：US20070155153A1

公开(公告)日：2007-07-05

申请号：US11649208

申请日：2007-01-04

申请人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

发明人： Tsutomu Okazaki ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

IPC分类号： H01L21/44

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

公开(公告)号：US06853022B2

公开(公告)日：2005-02-08

申请号：US10352987

申请日：2003-01-29

申请人： Tsuyoshi Koga ,  Yoshiyuki Ishigaki ,  Motoi Ashida ,  Yukio Maki ,  Yasuhiro Fujii ,  Tomohiro Hosokawa ,  Takashi Terada ,  Makoto Dei ,  Yasuichi Masuda

发明人： Tsuyoshi Koga ,  Yoshiyuki Ishigaki ,  Motoi Ashida ,  Yukio Maki ,  Yasuhiro Fujii ,  Tomohiro Hosokawa ,  Takashi Terada ,  Makoto Dei ,  Yasuichi Masuda

IPC分类号： H01L27/108 ,  G11C11/402 ,  G11C11/412 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C11/4023 ,  G11C11/412 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11 ,  H01L27/1108

摘要： A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

摘要翻译： 一种半导体存储器件，其主要存储部分是存储电荷作为二进制信息的电容器，以及控制向电容器的电荷输入/输出的存取晶体管，并且不需要刷新。 半导体存储器件包括具有存储节点的电容器，该存储节点位于半导体衬底之上，并且保持对应于存储的二进制信息的逻辑电平的电荷，位于半导体衬底表面上的存取晶体管，并控制累积在该半导体衬底表面上的电荷的输入/输出 电容器和位于半导体衬底上的锁存电路，并保持电容器存储节点的电位。 构成锁存电路的电路元件中的至少一个位于存取晶体管的上方。

公开(公告)号：US08174062B2

公开(公告)日：2012-05-08

申请号：US12504146

申请日：2009-07-16

申请人： Motoi Ashida

发明人： Motoi Ashida

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234

摘要： A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved.

摘要翻译： 半导体存储器件包括：半导体衬底; 第一杂质区; 第二杂质区; 一个通道区域 形成在所述第一杂质区一侧的主表面上的第一栅极; 第二栅极，形成在第二杂质区一侧的主表面上，第二绝缘膜被插入; 以及形成在所述第一栅极的侧表面上的第三绝缘膜。 第三绝缘膜和直接位于第三绝缘膜下方的半导体衬底之间的界面位于第二绝缘膜正下方的第二绝缘膜和半导体衬底的主表面之间的界面之上。 因此可以减少步骤的总数，并且实现更低的成本。

公开(公告)号：US07348637B2

公开(公告)日：2008-03-25

申请号：US11376142

申请日：2006-03-16

申请人： Motoi Ashida ,  Takashi Terada

发明人： Motoi Ashida ,  Takashi Terada

IPC分类号： H01L29/72

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.

摘要翻译： 一种包括多个CMOS晶体管的半导体器件，其中第一和第二晶体管共享共同的第一栅电极，第三和第四晶体管共享与第一栅电极相邻并平行的公共第二栅电极。 第一和第三晶体管共享共同的n型沟道MOS区，第二和第四晶体管共享公共p型沟道MOS区。 半导体器件具有连接n型沟道MOS区和p型沟道MOS区的导线。 所述导线的宽度大于所述第一和第二相邻栅电极之间的距离，并且所述导线的一部分设置在所述第一和第二栅电极中的至少一个的一部分的正上方，其间插入绝缘膜。