公开(公告)号：US6057558A

公开(公告)日：2000-05-02

申请号：US34344

申请日：1998-03-04

申请人： Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

发明人： Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/0847 ,  H01L29/0626 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7828 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238

摘要： In a silicon carbide semiconductor device such as a trench gate type power MOSFET, the film thickness and the impurity concentration of a thin film silicon carbide semiconductor layer formed on a trench side face to constitute an accumulation-type channel-forming region and enable the device to operate with a low gate voltage, low on-resistance and low power loss are set so that on impression of a reverse bias voltage a pn junction between a P-type epitaxial layer and an n.sup.- -type epitaxial layer undergoes avalanche breakdown before the thin film silicon carbide semiconductor layer undergoes punch-through. By this means it is possible to obtain a target high source-drain withstand voltage.

摘要翻译： 在诸如沟槽栅型功率MOSFET的碳化硅半导体器件中，形成在沟槽侧面上的薄膜碳化硅半导体层的膜厚度和杂质浓度构成积聚型沟道形成区域，并使器件 以低栅极电压操作，设置低导通电阻和低功率损耗，使得在反向偏置电压的印象上，P型外延层和n型外延层之间的pn结在其之前经历雪崩击穿 薄膜碳化硅半导体层进行穿通。 通过这种方式，可以获得目标高的源极 - 漏极耐受电压。

公开(公告)号：US6054752A

公开(公告)日：2000-04-25

申请号：US107507

申请日：1998-06-30

申请人： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

发明人： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/34 ,  H01L29/40

CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0638 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/1608

摘要： A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.

摘要翻译： 半导体器件包括：半导体衬底，包括形成在第一半导体层上的第一导电型第一半导体层和第二导电型第二半导体层。 在半导体衬底中形成用于控制在源电极和漏电极之间流动的电流的单元。 在单电池的周边区域形成沟槽，形成台面结构。 在第二沟槽的侧面上的绝缘膜与第一半导体层和第二半导体层之间形成场弛豫层，以使绝缘膜中的电场的集中化。

公开(公告)号：US06297100B1

公开(公告)日：2001-10-02

申请号：US09408185

申请日：1999-09-29

申请人： Rajesh Kumar ,  Masami Naito ,  Hiroki Nakamura ,  Yuichi Takeuchi

发明人： Rajesh Kumar ,  Masami Naito ,  Hiroki Nakamura ,  Yuichi Takeuchi

IPC分类号： H01L21336

CPC分类号： H01L29/66068 ,  H01L21/0445 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/7828 ,  Y10S438/931

摘要： In a vertical MOSFET, an inactive ion species is ion-implanted into a J-FET portion, a surface channel layer, and/or a base region. The inactive ion species fill intrinsic carbon vacancies or interact with interstitial Si atoms, which are possible origin or responsible for B-diffusion from the base region. Accordingly, the B-diffusion caused by the intrinsic carbon vacancies when the base region is formed is suppressed. The width of the J-FET portion is prevented from being decreased, thereby preventing an increase in resistance of the J-FET portion. Also, the conductive type of the surface channel layer is prevented from being inverted by diffused impurities.

摘要翻译： 在垂直MOSFET中，将非活性离子种离子注入到J-FET部分，表面沟道层和/或基极区域中。 非活性离子物质填充本征碳空位或与间隙Si原子相互作用，这是可能的起源或负责来自碱性区域的B扩散。 因此，抑制了形成基极区域时由本征碳空位引起的B扩散。 防止J-FET部分的宽度减小，从而防止J-FET部分的电阻增加。 此外，通过扩散的杂质防止了表面通道层的导电类型的反转。

公开(公告)号：US07541300B2

公开(公告)日：2009-06-02

申请号：US11826070

申请日：2007-07-12

申请人： Malhan Rajesh Kumar ,  Yuichi Takeuchi

发明人： Malhan Rajesh Kumar ,  Yuichi Takeuchi

IPC分类号： H01L21/00

CPC分类号： H01L29/7828 ,  H01L29/1608 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7397 ,  Y10S438/931

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and a bottom of the trench; an oxide film on the channel layer; a gate electrode on the oxide film; a first electrode connecting to the third semiconductor layer; and a second electrode connecting to the silicon carbide substrate. A position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film.

公开(公告)号：US20060284217A1

公开(公告)日：2006-12-21

申请号：US11501777

申请日：2006-08-10

申请人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

发明人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC分类号： H01L29/80

CPC分类号： H01L29/8083 ,  H01L29/1608

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

摘要翻译： 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

公开(公告)号：US07399676B2

公开(公告)日：2008-07-15

申请号：US11268612

申请日：2005-11-08

申请人： Malhan Rajesh Kumar ,  Yuichi Takeuchi

发明人： Malhan Rajesh Kumar ,  Yuichi Takeuchi

IPC分类号： H01L21/336 ,  H01L21/8242

CPC分类号： H01L29/7811 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7828

摘要： A method for manufacturing a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate and first to third semiconductor layers; forming a trench in a cell region of the semiconductor substrate; forming a fourth semiconductor layer in the trench; forming an oxide film in the trench such that a part of the fourth semiconductor layer on a sidewall of the trench is thermally oxidized; forming a gate electrode on the oxide film in the trench; forming a first electrode electrically connecting to the third semiconductor layer; and forming a first electrode electrically connecting to the silicon carbide substrate.

摘要翻译： 一种制造碳化硅半导体器件的方法包括以下步骤：制备包括碳化硅衬底和第一至第三半导体层的半导体衬底; 在所述半导体衬底的单元区域中形成沟槽; 在沟槽中形成第四半导体层; 在沟槽中形成氧化膜，使得沟槽侧壁上的第四半导体层的一部分被热氧化; 在沟槽中的氧化膜上形成栅电极; 形成电连接到所述第三半导体层的第一电极; 以及形成电连接到所述碳化硅衬底的第一电极。

公开(公告)号：US07582932B2

公开(公告)日：2009-09-01

申请号：US11268771

申请日：2005-11-08

申请人： Malhan Rajesh Kumar ,  Yuichi Takeuchi

发明人： Malhan Rajesh Kumar ,  Yuichi Takeuchi

IPC分类号： H01L31/0312

CPC分类号： H01L29/7828 ,  H01L29/1608 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7397 ,  Y10S438/931

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and a bottom of the trench; an oxide film on the channel layer; a gate electrode on the oxide film; a first electrode connecting to the third semiconductor layer; and a second electrode connecting to the silicon carbide substrate. A position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film.

摘要翻译： 碳化硅半导体器件包括：具有碳化硅衬底，第一半导体层，第二半导体层和第三半导体层的半导体衬底; 穿过第二和第三半导体层的沟槽到达第一半导体层; 在沟槽的侧壁和底部上的沟道层; 沟道层上的氧化膜; 氧化膜上的栅电极; 连接到第三半导体层的第一电极; 以及连接到碳化硅衬底的第二电极。 第一半导体层和第二半导体层之间的边界的位置被设置为低于氧化膜的最低位置。

公开(公告)号：US07141498B2

公开(公告)日：2006-11-28

申请号：US11159264

申请日：2005-06-23

申请人： Rajesh Kumar Malhan ,  Yuichi Takeuchi ,  Irina Nikitina ,  Konstantin Vassilevski ,  Nicholas Wright ,  Alton Horsfall

发明人： Rajesh Kumar Malhan ,  Yuichi Takeuchi ,  Irina Nikitina ,  Konstantin Vassilevski ,  Nicholas Wright ,  Alton Horsfall

IPC分类号： H01L21/44

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395

摘要： A method of forming an ohmic contact on a substrate composed of a wide-band gap semiconductor material includes: depositing a transition metal group metal on the substrate; annealing the substrate at a high temperature to cause a solid state chemical reaction between the substrate and the deposited metal that forms a modified layer in the substrate having modified properties different than the substrate, and by-products composed of a silicide and a nanocrystalline graphite layer; selectively etching the substrate to remove one or more of the by-products of the solid state chemical reaction from a surface of the substrate; and depositing a metal film composed of a transition group metal over the modified layer on the substrate to form the ohmic contact. The modified layer permits formation of the ohmic contact without high temperature annealing after depositing the metal film.

公开(公告)号：US20050145852A1

公开(公告)日：2005-07-07

申请号：US10995566

申请日：2004-11-24

申请人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

发明人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC分类号： H01L29/80 ,  H01L21/337 ,  H01L29/24 ,  H01L29/808 ,  H01L29/15

CPC分类号： H01L29/8083 ,  H01L29/1608

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

摘要翻译： 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

公开(公告)号：US07164154B2

公开(公告)日：2007-01-16

申请号：US10995566

申请日：2004-11-24

申请人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

发明人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC分类号： H01L29/15

CPC分类号： H01L29/8083 ,  H01L29/1608

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

摘要翻译： 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。