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31 条记录 (耗时 0.028 秒)

    Integrated circuits
    1.
    发明授权
    Integrated circuits 有权
    集成电路

    公开(公告)号：US08884341B2

    公开(公告)日：2014-11-11

    申请号：US13210962

    申请日：2011-08-16

    申请人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Chien-Tai Chan ,  King-Yuen Wong ,  Chien-Chang Su

    发明人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Chien-Tai Chan ,  King-Yuen Wong ,  Chien-Chang Su

    IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08

    CPC分类号： H01L29/7834 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66636

    摘要： An integrated circuit includes a gate electrode disposed over a substrate. A source/drain (S/D) region is disposed adjacent to the gate electrode. The S/D region includes a diffusion barrier structure disposed in a recess of the substrate. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode. The second portion is distant from the gate electrode. An N-type doped silicon-containing structure is disposed over the diffusion barrier structure. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. The second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.

    摘要翻译： 集成电路包括设置在基板上的栅电极。 源极/漏极（S / D）区域邻近栅电极设置。 S / D区域包括设置在基板的凹部中的扩散阻挡结构。 扩散阻挡结构包括第一部分和第二部分。 第一部分与栅电极相邻。 第二部分远离栅电极。 在扩散阻挡结构上设置N型掺杂的含硅结构。 扩散阻挡结构的第一部分被配置为部分地防止N型掺杂的含硅结构的N型掺杂剂扩散到衬底中。 扩散阻挡结构的第二部分被配置为基本上完全防止N型掺杂含硅结构的N型掺杂剂扩散到衬底中。

    Techniques for FinFET doping
    3.
    发明授权
    Techniques for FinFET doping 有权
    FinFET掺杂技术

    公开(公告)号：US08785286B2

    公开(公告)日：2014-07-22

    申请号：US12702803

    申请日：2010-02-09

    申请人： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

    发明人： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

    IPC分类号： H01L21/336 ,  H01L21/26 ,  H01L21/42 ,  H01L21/223

    CPC分类号： H01L29/66803 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/26526 ,  H01L21/26586

    摘要： A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.

    摘要翻译： 一种形成集成电路的方法包括提供半导体晶片，该半导体晶片包括在半导体晶片的表面上分配的半导体鳍; 在所述半导体鳍片的顶表面和侧壁上形成具有杂质的富掺杂层，其中所述杂质为n型或p型; 执行敲击植入以将杂质驱动到半导体鳍片中; 并除去富含掺杂剂的层。

    Techniques for FinFET Doping
    4.
    发明申请
    Techniques for FinFET Doping 有权
    FinFET掺杂技术

    公开(公告)号：US20110195555A1

    公开(公告)日：2011-08-11

    申请号：US12702803

    申请日：2010-02-09

    申请人： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

    发明人： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Mao-Rong Yeh ,  Da-Wen Lin

    IPC分类号： H01L21/336 ,  H01L21/265

    CPC分类号： H01L29/66803 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/26526 ,  H01L21/26586

    摘要： A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.

    摘要翻译： 一种形成集成电路的方法包括提供半导体晶片，该半导体晶片包括在半导体晶片的表面上分配的半导体鳍; 在所述半导体鳍片的顶表面和侧壁上形成具有杂质的富掺杂层，其中所述杂质为n型或p型; 执行敲击植入以将杂质驱动到半导体鳍片中; 并除去富含掺杂剂的层。

    STRUCTURE AND METHOD FOR THERMAL TREATMENT WITH EPITAXIAL SICP THERMAL STABILITY IMPROVEMENT
    7.
    发明申请
    STRUCTURE AND METHOD FOR THERMAL TREATMENT WITH EPITAXIAL SICP THERMAL STABILITY IMPROVEMENT 有权
    具有外源SICP热稳定性改进的热处理结构和方法

    公开(公告)号：US20130157431A1

    公开(公告)日：2013-06-20

    申请号：US13332011

    申请日：2011-12-20

    申请人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Tsan-Chun Wang

    发明人： Chun Hsiung Tsai ,  Su-Hao Liu ,  Tsan-Chun Wang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/2686 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

    摘要： The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet.

    摘要翻译： 本公开提供了在一个实施例中制造集成电路的方法。 该方法包括提供具有有源区的半导体衬底和设置在有源区中的半导体衬底上的第一栅叠层; 在所述半导体衬底上形成原位磷掺杂碳化硅（SiCP）特征并且设置在所述第一栅极叠层的侧面上; 用具有高k介电材料层的第二栅极堆叠代替第一栅极堆叠; 然后进行具有第一热小波和第二热小波的热分布的毫秒退火（MSA）处理。

    Epitaxial formation of source and drain regions
    10.
    发明授权
    Epitaxial formation of source and drain regions 有权
    源极和漏极区域的外延形成

    公开(公告)号：US09012310B2

    公开(公告)日：2015-04-21

    申请号：US13493626

    申请日：2012-06-11

    申请人： Chun Hsiung Tsai ,  Yi-Fang Pai

    发明人： Chun Hsiung Tsai ,  Yi-Fang Pai

    IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L27/088 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823425 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： Mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) are provided. The mechanisms eliminate dislocations near gate corners and gate corner defects (GCDs), and maintain transistor performance. The mechanisms described involve using a post-deposition etch to remove residual dislocations near gate corners after a cyclic deposition and etching (CDE) process is used to fill a portion of the recess regions with an epitaxially grown silicon-containing material. The mechanisms described also minimize the growth of dislocations near gate corners during the CDE process. The remaining recess regions may be filled by another silicon-containing layer deposited by an epitaxial process without forming dislocations near gate corners. The embodiments described enable gate corners to be free of dislocation defects, preserve the device performance from degradation, and widen the process window of forming S/D regions without gate corner defects and chamber matching issues.

    摘要翻译： 提供了用于形成场效应晶体管（FET）的源极/漏极（S / D）区域的机构。 这些机制消除了栅极拐角和栅极角缺陷（GCD）附近的位错，并保持了晶体管的性能。 所描述的机理涉及在循环沉积和蚀刻（CDE）工艺用外延生长的含硅材料填充一部分凹陷区域之后使用后沉积蚀刻去除栅极角附近的残留位错。 所描述的机理还使CDE过程中门角附近的位错生长最小化。 剩余的凹陷区域可以由通过外延工艺沉积的另一个含硅层填充，而不会在栅极拐角附近形成位错。 所描述的实施方式使得栅极角不受位错缺陷，保护器件性能不受降解，并且扩大了形成S / D区域的过程窗口，而没有门角缺陷和腔室匹配问题。