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公开(公告)号：US10256297B2
公开(公告)日：2019-04-09
申请号：US15365954
申请日：2016-12-01
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L21/28 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/16 , H01L29/24 , H01L29/45 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78 , H01L21/285 , H01L21/768 , H01L29/161 , H01L29/165
Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.
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公开(公告)号：US10177156B2
公开(公告)日：2019-01-08
申请号：US15491939
申请日：2017-04-19
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L27/11 , H01L27/12 , H01L27/092 , H01L29/78 , H01L23/535 , H01L29/66 , H01L21/8238
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate includes a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.
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公开(公告)号：US09865654B1
公开(公告)日：2018-01-09
申请号：US15399747
申请日：2017-01-06
Applicant: UNITED MICROELECTRONICS CORP.
CPC classification number: H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144
Abstract: A semiconductor structure includes a front side and a back side opposite to the front side, at least a transistor device formed on the front side of the substrate, and an adjustable resistor formed on the back side of the substrate. The adjustable resistor includes at least a phase change material PCM layer.
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公开(公告)号：US10062734B2
公开(公告)日：2018-08-28
申请号：US15849563
申请日：2017-12-20
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L21/8234 , H01L45/00 , H01L27/24 , H01L29/786
CPC classification number: H01L21/82345 , H01L29/435 , H01L29/4908 , H01L29/7869
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer near one side of the gate dielectric layer and a drain layer near another side of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.
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公开(公告)号：US10008614B1
公开(公告)日：2018-06-26
申请号：US15464353
申请日：2017-03-21
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L29/786 , H01L29/417 , H01L29/45 , H01L29/66
CPC classification number: H01L29/78696 , H01L27/1225 , H01L29/1054 , H01L29/41733 , H01L29/78648 , H01L29/7869
Abstract: A dual channel transistor includes a first gate electrode, a second gate electrode, a first gate insulation layer, a second gate insulation layer, a silicon semiconductor channel layer, and an oxide semiconductor channel layer. The first gate insulation layer is disposed on the first gate electrode. The silicon semiconductor channel layer is disposed on the first gate insulation layer. The oxide semiconductor channel layer is disposed on the silicon semiconductor channel layer. The second gate insulation layer is disposed on the oxide semiconductor channel layer. The second gate electrode is disposed on the second gate insulation layer.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09806191B1
公开(公告)日：2017-10-31
申请号：US15289982
申请日：2016-10-11
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L29/10 , H01L29/12 , H01L29/78 , H01L29/66 , H01L29/08 , H01L29/423 , H01L21/441 , H01L21/467 , H01L29/24
CPC classification number: H01L29/7827 , H01L21/441 , H01L21/467 , H01L29/0847 , H01L29/1037 , H01L29/24 , H01L29/42364 , H01L29/42392 , H01L29/66969 , H01L29/7869
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a source layer; removing part of the source layer to form a first opening; forming a first channel layer in the first opening; forming a gate layer around the first channel layer and on the source layer; forming a drain layer on the gate layer and the first channel layer; removing part of the drain layer to form a second opening; and forming a second channel layer in the second opening.
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公开(公告)号：US10978556B2
公开(公告)日：2021-04-13
申请号：US16280047
申请日：2019-02-20
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L29/06 , H01L29/78 , H01L29/165 , H01L21/28 , H01L21/285 , H01L21/768 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/24 , H01L29/45 , H01L29/66 , H01L29/51 , H01L29/10 , H01L29/49
Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.
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公开(公告)号：US10347645B2
公开(公告)日：2019-07-09
申请号：US16207171
申请日：2018-12-02
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L27/11 , H01L27/12 , H01L23/535 , H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L21/8234
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate comprises a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.
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公开(公告)号：US10062701B2
公开(公告)日：2018-08-28
申请号：US15361070
申请日：2016-11-24
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L27/11 , G11C11/412 , G11C11/419
CPC classification number: H01L27/1104 , G11C11/412 , G11C11/4125 , G11C11/419 , H01L27/0207 , H01L27/1116
Abstract: The present invention provides a SRAM unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second doped regions. The transistors are disposed on the semiconductor substrate, and include a first gate line and a second gate line. The first well is disposed in the semiconductor substrate, and the first well has a first conductive type, wherein the first gate line and the second gate line extend onto the first well. The first doped regions are disposed in the first well at two sides of the first gate line, and the second doped regions are disposed in the first well at two sides of the second gate line.
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公开(公告)号：US09887238B1
公开(公告)日：2018-02-06
申请号：US15413349
申请日：2017-01-23
Applicant: UNITED MICROELECTRONICS CORP.
IPC: H01L45/00 , H01L21/8234 , H01L27/24 , H01L29/786
CPC classification number: H01L27/2436 , H01L21/82345 , H01L29/7869 , H01L45/065 , H01L45/122 , H01L45/126 , H01L45/144 , H01L45/1608
Abstract: A semiconductor device and a method for fabricating the semiconductor device have been provided. The method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer and a drain layer adjacent two sides of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.
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