公开(公告)号：US20150333170A1

公开(公告)日：2015-11-19

申请号：US14650176

申请日：2013-12-19

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Inventor： Junhong Li ,  Ping Li

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66712 ,  H01L29/7812 ,  H01L29/7816

Abstract: Provided is a lateral power device having low specific ON-resistance and using a high-dielectric constant socket structure and a manufacturing method therefor, which relate to semiconductor power devices. A source electrode (8) of the device is of a first conduction type, and a channel region (6), a silicon substrate (4) and an ohmic contact heavily-doped region are of a second conduction type; at least two isolation regions are arranged in an embedded manner in a drift region (1); between the isolation regions are the drift region (1) and the channel region (6); each isolation region extends from the source electrode (8) to a drain electrode (11); high-dielectric constant material strips (3) and first insulation dielectric layers (10) form boundaries of the bottoms and sidewalls of the isolation regions; the isolation regions are filled with a first filling material (2), a second insulation dielectric layer (9) is arranged on the upper surface of the drift region (1) and the upper surfaces of the isolation regions, and a gate electrode (5) directly contacts the first filling material (2) via holes on the second insulation dielectric layer (9); and a source electrode lead-out wire (16) and a drain electrode lead-out wire (12) directly contact the source electrode (8) and the drain electrode (11) respectively via the holes on the second insulation dielectric layer (9). The area of a power device can be greatly reduced on the premise of not reducing the withstand voltage and not increasing the specific ON-resistance.

Abstract translation: 本发明提供一种具有低比导通电阻和使用涉及半导体功率器件的高介电常数插座结构及其制造方法的侧向功率器件。 器件的源极（8）是第一导电类型，沟道区（6），硅衬底（4）和欧姆接触重掺杂区是第二导电类型; 至少两个隔离区域以嵌入的方式布置在漂移区域（1）中; 在隔离区之间是漂移区（1）和沟道区（6）; 每个隔离区域从源电极（8）延伸到漏电极（11）; 高介电常数材料条（3）和第一绝缘电介质层（10）形成隔离区的底部和侧壁的边界; 隔离区域填充有第一填充材料（2），在漂移区域（1）的上表面和隔离区域的上表面上设置第二绝缘电介质层（9）和栅电极（5） ）通过第二绝缘介电层（9）上的孔直接接触第一填充材料（2）; 并且源电极引出线（16）和漏电极引出线（12）分别经由第二绝缘介电层（9）上的孔直接接触源电极（8）和漏电极（11） 。 在不降低耐压且不增加特定导通电阻的前提下，功率器件的面积可以大大降低。

公开(公告)号：US11145754B2

公开(公告)日：2021-10-12

申请号：US16699760

申请日：2019-12-02

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Inventor： Yongbo Liao ,  Ping Li ,  Rongzhou Zeng ,  Qingwei Zhang ,  Xia Li

IPC: H01L29/76 ,  H01L29/51 ,  H01L29/08 ,  H01L29/45

Abstract: The methods of gate extraction and injection FET and channel carrier quantity control related to microelectronics technology and semiconductor technology. The gate extraction and injection FET of the invention is provided with a source, a drain, a gate and a channel semiconductor area on the insulating layer. A gate dielectric layer is arranged between the gate and the channel semiconductor region, wherein, the gate dielectric layer is a thin film material with resistance values of 103-1016Ω and the channel semiconductor region is a two-dimensional semiconductor or a three-dimensional semiconductor with two-dimensional semiconductor material characteristics (1-10 cellular crystal layers). The advantages of the invention are that the power consumptions of the devices and the integrated circuits can be greatly reduced by a few orders of magnitude.

公开(公告)号：US09324855B2

公开(公告)日：2016-04-26

申请号：US14650176

申请日：2013-12-19

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Inventor： Junhong Li ,  Ping Li

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66712 ,  H01L29/7812 ,  H01L29/7816

Abstract: Provided is a lateral power device having low specific ON-resistance and using a high-dielectric constant socket structure and a manufacturing method therefor, which relate to semiconductor power devices. A source electrode (8) of the device is of a first conduction type, and a channel region (6), a silicon substrate (4) and an ohmic contact heavily-doped region are of a second conduction type; at least two isolation regions are arranged in an embedded manner in a drift region (1); between the isolation regions are the drift region (1) and the channel region (6); each isolation region extends from the source electrode (8) to a drain electrode (11); high-dielectric constant material strips (3) and first insulation dielectric layers (10) form boundaries of the bottoms and sidewalls of the isolation regions; the isolation regions are filled with a first filling material (2), a second insulation dielectric layer (9) is arranged on the upper surface of the drift region (1) and the upper surfaces of the isolation regions, and a gate electrode (5) directly contacts the first filling material (2) via holes on the second insulation dielectric layer (9); and a source electrode lead-out wire (16) and a drain electrode lead-out wire (12) directly contact the source electrode (8) and the drain electrode (11) respectively via the holes on the second insulation dielectric layer (9). The area of a power device can be greatly reduced on the premise of not reducing the withstand voltage and not increasing the specific ON-resistance.

Abstract translation: 本发明提供一种具有低比导通电阻和使用涉及半导体功率器件的高介电常数插座结构及其制造方法的侧向功率器件。 器件的源极（8）是第一导电类型，沟道区（6），硅衬底（4）和欧姆接触重掺杂区是第二导电类型; 至少两个隔离区域以嵌入的方式布置在漂移区域（1）中; 在隔离区之间是漂移区（1）和沟道区（6）; 每个隔离区域从源电极（8）延伸到漏电极（11）; 高介电常数材料条（3）和第一绝缘电介质层（10）形成隔离区的底部和侧壁的边界; 隔离区域填充有第一填充材料（2），在漂移区域（1）的上表面和隔离区域的上表面上设置第二绝缘电介质层（9）和栅电极（5） ）通过第二绝缘介电层（9）上的孔直接接触第一填充材料（2）; 并且源电极引出线（16）和漏电极引出线（12）分别经由第二绝缘介电层（9）上的孔直接接触源电极（8）和漏电极（11） 。 在不降低耐压且不增加特定导通电阻的前提下，功率器件的面积可以大大降低。

公开(公告)号：US11621349B2

公开(公告)日：2023-04-04

申请号：US17367573

申请日：2021-07-05

Applicant: University of Electronic Science and Technology of China

Inventor： Ping Li ,  Yongbo Liao ,  Xianghe Zeng ,  Yaosen Li ,  Ke Feng ,  Chenxi Peng ,  Zhaoxi Hu ,  Fan Lin ,  Xuanlin Xiong ,  Tao He

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/10

Abstract: A nano-wall integrated circuit structure with high integration density is disclosed, which relates to the fields of microelectronic technology and integrated circuits (IC). Based on the different device physical principles with MOSFETs in traditional ICs, the nano-wall integrated circuit unit structure (Nano-Wall FET, referred to as NWaFET) with high integration density can improve the integration of the IC, significantly shorten the channel length, improve the flexibility of the device channel width-to-length ratio adjustment, and save chip area.

公开(公告)号：US11335785B2

公开(公告)日：2022-05-17

申请号：US17126069

申请日：2020-12-18

Applicant: University of Electronic Science and Technology of China

Inventor： Ping Li ,  Yongbo Liao ,  Chenxi Peng ,  Yaosen Li ,  Ruihong Nie ,  Ke Feng ,  Xianghe Zeng ,  Ruifeng Tang ,  Jiarui Zou ,  Zhaoxi Hu ,  Fan Lin

IPC: H01L29/02 ,  H01L29/417 ,  H01L29/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H02M7/537

Abstract: A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.