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公开(公告)号:US20200075711A1
公开(公告)日:2020-03-05
申请号:US16159726
申请日:2018-10-15
发明人: Yu-Hua Chen , Fu-Yang Chen , Chun-Hsien Chien , Chien-Chou Chen , Wei-Ti Lin
IPC分类号: H01L49/02 , H01L23/522 , H01L23/532 , H01L23/15 , H01L23/498
摘要: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.
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公开(公告)号:US20200043839A1
公开(公告)日:2020-02-06
申请号:US16167540
申请日:2018-10-23
发明人: Cheng-Ta Ko , Kai-Ming Yang , Yu-Hua Chen , Tzyy-Jang Tseng
IPC分类号: H01L23/498
摘要: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills in the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills in the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.
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公开(公告)号:US20190250502A1
公开(公告)日:2019-08-15
申请号:US16395244
申请日:2019-04-26
发明人: Pu-Ju Lin , Shih-Lian Cheng , Yu-Hua Chen , Cheng-Ta Ko , Jui-Jung Chien , Wei-Tse Ho
IPC分类号: G03F1/50 , G03F7/20 , H05K3/42 , H05K3/18 , H05K3/12 , H05K3/10 , H05K3/00 , G01K15/00 , G01K7/24 , H05K3/24 , H05K3/06
CPC分类号: G03F1/50 , G01K7/24 , G01K15/007 , G03F7/2032 , G03F7/2047 , H05K3/0023 , H05K3/064 , H05K3/107 , H05K3/1275 , H05K3/182 , H05K3/241 , H05K3/422 , Y10T29/49124
摘要: A mask structure and a manufacturing method of the mask structure are provided. The mask structure includes a transparent substrate, a patterned metal layer, and a plurality of microlens structures. The patterned metal layer is disposed on the transparent substrate and exposing a portion of the transparent substrate. The microlens structures are disposed on the transparent substrate exposed by a portion of the patterned metal layer and being in contact with the portion of the patterned metal layer.
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公开(公告)号:US10324370B2
公开(公告)日:2019-06-18
申请号:US15256757
申请日:2016-09-06
发明人: Pu-Ju Lin , Shih-Lian Cheng , Yu-Hua Chen , Cheng-Ta Ko , Jui-Jung Chien , Wei-Tse Ho
IPC分类号: H05K3/00 , G03F1/50 , H05K3/06 , H05K3/24 , G01K7/24 , G01K15/00 , H05K3/10 , H05K3/12 , H05K3/18 , H05K3/42 , G03F7/20
摘要: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.
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公开(公告)号:US10211139B2
公开(公告)日:2019-02-19
申请号:US15287729
申请日:2016-10-06
发明人: Tzyy-Jang Tseng , Yu-Hua Chen , Ra-Min Tain
IPC分类号: H01L23/498 , H01L23/48 , H01L25/10 , H01L21/48 , H01L23/367 , H01L23/31 , C25D5/02 , C25D5/34 , C25D5/48 , C25D7/12 , H05K1/11 , H05K3/46 , H01L23/36 , H05K3/42
摘要: A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate.
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公开(公告)号:US10083901B2
公开(公告)日:2018-09-25
申请号:US15853926
申请日:2017-12-25
发明人: Yu-Hua Chen , Cheng-Ta Ko
IPC分类号: H05K3/46 , H01L23/498 , H01L21/48 , H01L23/00
CPC分类号: H01L23/49822 , H01L21/4853 , H01L21/4857 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/562 , H05K3/4682 , H05K3/4688 , H05K2201/096 , H05K2201/10378
摘要: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
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公开(公告)号:US20170194249A1
公开(公告)日:2017-07-06
申请号:US15468087
申请日:2017-03-23
发明人: Yu-Hua Chen , Wei-Chung Lo , Dyi-Chung Hu , Chang-Hong Hsieh
IPC分类号: H01L23/522 , H01L21/48 , H01L25/04 , H01L23/498
CPC分类号: H01L23/5226 , H01L21/4857 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L25/04 , H01L2924/0002 , H01L2924/00
摘要: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
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公开(公告)号:US20220287182A1
公开(公告)日:2022-09-08
申请号:US17826178
申请日:2022-05-27
发明人: Tzyy-Jang Tseng , Yu-Hua Chen , Chun-Hsien Chien , Wen-Liang Yeh , Ra-Min Tain
摘要: An embedded component structure includes a board, an electronic component, and a dielectric material layer. The board has a through cavity. The board includes an insulating core layer and a conductive member. The insulating core layer has a first surface and a second surface opposite thereto. The through cavity penetrates the insulating core layer. The conductive member extends from a portion of the first surface along a portion of the side wall of the through cavity to a portion of the second surface. The electronic component includes an electrode. The electronic component is disposed in the through cavity. The dielectric material layer is at least filled in the through cavity. The connection circuit layer covers and contacts the conductive member and the electrode. A manufacturing method of an embedded component structure is also provided.
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公开(公告)号:US11410940B2
公开(公告)日:2022-08-09
申请号:US17170736
申请日:2021-02-08
发明人: Pu-Ju Lin , Cheng-Ta Ko , Yu-Hua Chen , Tzyy-Jang Tseng , Ra-Min Tain
摘要: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
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公开(公告)号:US10957658B2
公开(公告)日:2021-03-23
申请号:US16866530
申请日:2020-05-04
发明人: Pu-Ju Lin , Cheng-Ta Ko , Yu-Hua Chen , Tzyy-Jang Tseng , Ra-Min Tain
摘要: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
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