公开(公告)号：US20230124913A1

公开(公告)日：2023-04-20

申请号：US17705405

申请日：2022-03-28

Applicant: Unimicron Technology Corp.

Inventor： Heng-Ming Nien ,  Chih-Chiang Lu ,  Chih-Kai Chan ,  Shih-Lian Cheng

IPC: C25D5/00 ,  C25D21/12

Abstract: An electroplating apparatus includes an anode and a cathode, a power supply, a regulating plate, and a controller. The power supply is electrically connected to the anode and the cathode. The regulating plate is disposed between the anode and the cathode. The regulating plate includes an insulation grid plate and a plurality of wires. The controller is electrically connected to the plurality of wires to control a state of an electromagnetic field around the plurality of wires. An electroplating method is also provided.

公开(公告)号：US20230124732A1

公开(公告)日：2023-04-20

申请号：US17745809

申请日：2022-05-16

Applicant: Unimicron Technology Corp.

Inventor： Heng-Ming Nien ,  Chih-Chiang Lu ,  Cho-Ying Wu ,  Shih-Lian Cheng

IPC: C25D5/00

Abstract: An electroplating apparatus including an anode and a cathode, a power supply, and a regulating plate is provided. The power supply is electrically connected to the anode and the cathode. The regulating plate is arranged between the anode and the cathode. The regulating plate includes an insulating grid plate and a plurality of magnetic components. The plurality of magnetic components are uniformly and randomly arranged on the insulating grid plate. An electroplating method is also provided.

公开(公告)号：US20170273189A1

公开(公告)日：2017-09-21

申请号：US15252247

申请日：2016-08-31

Applicant: Unimicron Technology Corp.

Inventor： Shih-Lian Cheng

IPC: H05K3/06 ,  H05K3/10

CPC classification number: H05K3/064 ,  G03F7/0002 ,  G03F7/162 ,  G03F7/20 ,  H05K1/115 ,  H05K3/0023 ,  H05K3/06 ,  H05K3/108 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/091 ,  H05K2203/0108 ,  H05K2203/0369 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/0562 ,  Y10T29/49124

Abstract: A manufacturing method of a circuit board and a piezochromic stamp are provided. A circuit pattern is formed on a dielectric substrate. A dielectric layer having a hole or a conductive via and covering the circuit pattern is formed on the dielectric substrate. A conductive seed layer is formed on the dielectric layer. A photoresist layer is formed on the conductive seed layer. A piezochromic stamp is imprinted on the photoresist layer, wherein when the pressing side of the piezochromic stamp is in contact with the conductive seed layer, the light transmittance effect thereof is changed to blocking or allowing light having a specific wavelength to pass through. A patterned photoresist layer is formed by using the piezochromic stamp as a mask. A patterned metal layer is formed on the exposed conductive seed layer. The patterned photoresist layer and the conductive seed layer are removed.

公开(公告)号：US08955218B2

公开(公告)日：2015-02-17

申请号：US14073846

申请日：2013-11-06

Applicant: Unimicron Technology Corp.

Inventor： Tsung-Yuan Chen ,  Shih-Lian Cheng

IPC: H01R9/00 ,  H05K3/40 ,  H01L23/498 ,  H01L21/48 ,  H05K3/46 ,  H05K3/10 ,  H01L23/00 ,  H05K3/34

CPC classification number: H05K3/4038 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K3/10 ,  H05K3/3436 ,  H05K3/4644 ,  H05K3/4694 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.

Abstract translation: 封装基板包括芯层，第一介电层，第二电路图案，第一焊接掩模和绝缘层。 第一电路图案设置在芯层的第一表面上。 第一电介质层覆盖第一电路图案。 第二电路图案位于第一电介质层上，第二电路图案包括在芯片安装区域内的互连电路图案。 第一焊接掩模覆盖芯片安装区域外的第二电路图案的一部分。 绝缘层覆盖芯片安装区域和互连电路图案。 多个嵌入式焊盘位于绝缘层的上表面上。

公开(公告)号：US20240414850A1

公开(公告)日：2024-12-12

申请号：US18404845

申请日：2024-01-04

Applicant: Unimicron Technology Corp.

Inventor： Chin-Sheng Wang ,  Ra-Min Tain ,  Chih-Kai Chan ,  Shih-Lian Cheng

IPC: H05K3/18 ,  H05K1/09 ,  H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/34

Abstract: A circuit board structure includes a core layer, at least one electroplating metal layer, at least one dielectric layer and at least one conductive metal layer. The core layer includes at least one dielectric portion and at least one metal portion. The electroplating metal layer is disposed on at least one of a first surface and a second surface of the core layer, exposing a portion of at least one of the first surface and the second surface and at least connecting the at least one metal part. The dielectric layer is disposed on at least one of the first surface and the second surface and on the electroplating metal layer. The dielectric layer has at least one opening exposing a portion of the electroplating metal layer. The conductive metal layer is disposed in the opening of the dielectric layer and is correspondingly connected to the electroplating metal layer.

公开(公告)号：US20230156909A1

公开(公告)日：2023-05-18

申请号：US17873153

申请日：2022-07-26

Applicant: Unimicron Technology Corp.

Inventor： Shih-Lian Cheng

IPC: H05K1/02

CPC classification number: H05K1/0222 ,  H05K1/024 ,  H05K2201/09536 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096

Abstract: A circuit board structure includes a first dielectric layer, first and second inner circuit layers, a conductive connection layer, a second dielectric layer, two third dielectric layers, third and fourth inner circuit layers, two conductive through vias, first and second annular retaining walls, two fourth dielectric layers, first and second external circuit layers, and third and fourth annular retaining walls. The conductive through vias penetrate the third and second dielectric layers and electrically connect the third and fourth inner circuit layers. The first and second annular retaining walls surround the conductive through vias and electrically connect the third and first and the fourth and second inner circuit layers. The third and fourth annular retaining walls are respectively disposed in the fourth dielectric layers and electrically connect the first external circuit layer and the third inner circuit layer and the second external circuit layer and the fourth inner circuit layer.

公开(公告)号：US20190250502A1

公开(公告)日：2019-08-15

申请号：US16395244

申请日：2019-04-26

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC: G03F1/50 ,  G03F7/20 ,  H05K3/42 ,  H05K3/18 ,  H05K3/12 ,  H05K3/10 ,  H05K3/00 ,  G01K15/00 ,  G01K7/24 ,  H05K3/24 ,  H05K3/06

CPC classification number: G03F1/50 ,  G01K7/24 ,  G01K15/007 ,  G03F7/2032 ,  G03F7/2047 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/107 ,  H05K3/1275 ,  H05K3/182 ,  H05K3/241 ,  H05K3/422 ,  Y10T29/49124

Abstract: A mask structure and a manufacturing method of the mask structure are provided. The mask structure includes a transparent substrate, a patterned metal layer, and a plurality of microlens structures. The patterned metal layer is disposed on the transparent substrate and exposing a portion of the transparent substrate. The microlens structures are disposed on the transparent substrate exposed by a portion of the patterned metal layer and being in contact with the portion of the patterned metal layer.

公开(公告)号：US10324370B2

公开(公告)日：2019-06-18

申请号：US15256757

申请日：2016-09-06

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC: H05K3/00 ,  G03F1/50 ,  H05K3/06 ,  H05K3/24 ,  G01K7/24 ,  G01K15/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/18 ,  H05K3/42 ,  G03F7/20

Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.

公开(公告)号：US10271433B2

公开(公告)日：2019-04-23

申请号：US14855404

申请日：2015-09-16

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

IPC: H05K3/30 ,  H05K3/00 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K3/06 ,  H05K3/42 ,  H05K3/46

Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.

公开(公告)号：US20170273186A1

公开(公告)日：2017-09-21

申请号：US15255150

申请日：2016-09-02

Applicant: Unimicron Technology Corp.

Inventor： Shih-Lian Cheng

IPC: H05K3/00 ,  H05K3/10 ,  H05K3/46

CPC classification number: H05K3/064 ,  G03F7/0002 ,  G03F7/162 ,  G03F7/20 ,  H05K1/115 ,  H05K3/0023 ,  H05K3/06 ,  H05K3/108 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/091 ,  H05K2203/0108 ,  H05K2203/0369 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/0562 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: A manufacturing method of a circuit board including the following steps is provided. A carrier substrate is provided. A patterned photoresist layer is formed on the carrier substrate. An adhesive layer is formed on the top surface of the patterned photoresist layer. A dielectric substrate is provided. A circuit pattern and a dielectric layer covering the circuit pattern are formed on the dielectric substrate, wherein the dielectric layer has an opening exposing a portion of the circuit pattern. The adhesive layer is adhered to the dielectric layer in a direction that the adhesive layer faces of the dielectric layer. The carrier substrate is removed. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed. The adhesive layer is removed.