公开(公告)号：US20220069102A1

公开(公告)日：2022-03-03

申请号：US17523946

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US10366896B2

公开(公告)日：2019-07-30

申请号：US15688852

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.

公开(公告)号：US11929418B2

公开(公告)日：2024-03-12

申请号：US17524723

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/76838 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US11881518B2

公开(公告)日：2024-01-23

申请号：US17523946

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L29/4966 ,  H01L21/76838 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US20190043725A1

公开(公告)日：2019-02-07

申请号：US15688852

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/28167 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.

公开(公告)号：US08692334B2

公开(公告)日：2014-04-08

申请号：US13949230

申请日：2013-07-24

Applicant: United Microelectronics Corp.

Inventor： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

IPC: H01L21/70

CPC classification number: H01L27/0629

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract translation: 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

公开(公告)号：US11239082B2

公开(公告)日：2022-02-01

申请号：US16438416

申请日：2019-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.

公开(公告)号：US20190295849A1

公开(公告)日：2019-09-26

申请号：US16438416

申请日：2019-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.

公开(公告)号：US10170573B1

公开(公告)日：2019-01-01

申请号：US15730748

申请日：2017-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ting Chiang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chih-Wei Lin ,  Bo-Yu Su ,  Yen-Liang Wu ,  I-Fan Chang ,  Jui-Ming Yang ,  Wen-Tsung Chang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a metal gate on the substrate, and a first inter-layer dielectric (ILD) layer around the metal gate. A top surface of the metal gate is lower than a top surface of the ILD layer thereby forming a recessed region atop the metal gate. A mask layer is disposed in the recessed region. A void is formed in the mask layer within the recessed region. A second ILD layer is disposed on the mask layer and the first ILD layer. A contact hole extends into the second ILD layer and the mask layer. The contact hole exposes the top surface of the metal gate and communicates with the void. A conductive layer is disposed in the contact hole and the void.

公开(公告)号：US09240459B2

公开(公告)日：2016-01-19

申请号：US13773635

申请日：2013-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hung Huang ,  Jie-Ning Yang ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Po-Jui Liao ,  Shih-Chang Chang

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/76801 ,  H01L21/76834 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成层叠结构。 形成接触蚀刻停止层以覆盖层叠结构和基板。 在衬底上形成材料层并暴露覆盖层叠结构的接触蚀刻停止层的顶部。 顶部被纠正。