中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.012 seconds)

    METAL GATE STRUCTURE AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    METAL GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220069102A1

    公开(公告)日：2022-03-03

    申请号：US17523946

    申请日：2021-11-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

    IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08890218B2

    公开(公告)日：2014-11-18

    申请号：US13892324

    申请日：2013-05-13

    Applicant: United Microelectronics Corp.

    Inventor： Chu-Chun Chang ,  Chun-Mao Chiou ,  Chiu-Te Lee

    IPC: H01L29/76 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7843

    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property.

    Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 设置在所述基板上的栅极结构; 设置在所述栅极结构的侧壁上的第一间隔物; 设置在所述第一间隔件周围的第二间隔件，其中所述第二间隔件包括在所述L形盖层上的L形盖层和盖层; 设置在所述基板中的与所述第二间隔物的两侧相邻的源极/漏极; 以及设置在所述基板上以覆盖所述栅极结构的CESL，其中所述第二间隔物和所述CESL的至少一部分包含相同的化学组成和/或物理性质。

    Through silicon via and method of forming the same
    3.
    发明授权
    Through silicon via and method of forming the same 有权
    通过硅通孔及其形成方法

    公开(公告)号：US08841755B2

    公开(公告)日：2014-09-23

    申请号：US13947125

    申请日：2013-07-22

    Applicant: United Microelectronics Corp.

    Inventor： Kuo-Hsiung Huang ,  Chun-Mao Chiou ,  Hsin-Yu Chen ,  Yu-Han Tsai ,  Ching-Li Yang ,  Home-Been Cheng

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/525

    CPC classification number: H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.

    Abstract translation: 本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。 绝缘层设置在通孔开口的表面上。 阻挡层设置在绝缘层的表面上。 缓冲层设置在阻挡层的表面上。 导电电极设置在缓冲层的表面上，通孔开口的其余部分被导电电极完全填充。 缓冲层的一部分还在第二表面的一侧覆盖导电电极的表面，并且所述部分与第二表面平齐。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12148796B2

    公开(公告)日：2024-11-19

    申请号：US18235358

    申请日：2023-08-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

    IPC: H01L29/06 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

    RESISTOR INTEGRATED WITH TRANSISTOR HAVING METAL GATE
    7.
    发明申请
    RESISTOR INTEGRATED WITH TRANSISTOR HAVING METAL GATE 有权
    电容器与带有金属栅的晶体管集成

    公开(公告)号：US20130307084A1

    公开(公告)日：2013-11-21

    申请号：US13949230

    申请日：2013-07-24

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Mao Chiou ,  Ti-Bin Chen ,  Tsung-Min Kuo ,  Shyan-Liang Chou ,  Yao-Chang Wang ,  Chi-Sheng Tseng ,  Jie-Ning Yang ,  Po-Jui Liao

    IPC: H01L27/06

    CPC classification number: H01L27/0629

    Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

    Abstract translation: 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130256765A1

    公开(公告)日：2013-10-03

    申请号：US13892324

    申请日：2013-05-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chu-Chun Chang ,  Chun-Mao Chiou ,  Chiu-Te Lee

    IPC: H01L29/78

    CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7843

    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property.

    Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 设置在所述基板上的栅极结构; 设置在所述栅极结构的侧壁上的第一间隔物; 设置在所述第一间隔件周围的第二间隔件，其中所述第二间隔件包括在所述L形盖层上的L形盖层和盖层; 设置在所述基板中的与所述第二间隔物的两侧相邻的源极/漏极; 以及设置在所述基板上以覆盖所述栅极结构的CESL，其中所述第二间隔物和所述CESL的至少一部分包含相同的化学组成和/或物理性质。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11764261B2

    公开(公告)日：2023-09-19

    申请号：US17670528

    申请日：2022-02-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

    IPC: H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/0649 ,  H01L29/7851

    Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11289572B1

    公开(公告)日：2022-03-29

    申请号：US17100963

    申请日：2020-11-23

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

    IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Patent Agency Ranking