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公开(公告)号：US10686079B1
公开(公告)日：2020-06-16
申请号：US16243014
申请日：2019-01-08
发明人： Chih-Yi Wang , Cheng-Pu Chiu , Huang-Ren Wei , Tien-Shan Hsu , Chi-Sheng Tseng , Yao-Jhan Wang
IPC分类号： H01L29/76 , H01L29/78 , H01L29/423 , H01L29/66 , H01L29/49 , H01L29/417 , H01L21/3213 , H01L21/8234
摘要： A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.
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公开(公告)号：US20240243124A1
公开(公告)日：2024-07-18
申请号：US18110353
申请日：2023-02-15
发明人： Chih-Wei Yang , Shih-Min Lu , Chi-Sheng Tseng , Yao-Jhan Wang , Chun-Hsien Lin
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/823456
摘要： A method for fabricating a semiconductor device includes the steps of first forming a first gate structure on a substrate and then forming a first epitaxial layer adjacent to the first gate structure. Preferably, a top surface of the first epitaxial layer includes a first curve, a second curve, and a third curve connecting the first curve and the second curve, in which the first curve and the second curve include curves concave downward while the third curve includes a curve concave upward.
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公开(公告)号：US09240459B2
公开(公告)日：2016-01-19
申请号：US13773635
申请日：2013-02-22
发明人： Kuang-Hung Huang , Jie-Ning Yang , Yao-Chang Wang , Chi-Sheng Tseng , Po-Jui Liao , Shih-Chang Chang
IPC分类号： H01L29/66 , H01L21/768 , H01L29/49 , H01L29/51
CPC分类号： H01L29/66545 , H01L21/76801 , H01L21/76834 , H01L29/4966 , H01L29/517 , H01L29/6653
摘要： A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.
摘要翻译： 半导体工艺包括以下步骤。 在基板上形成层叠结构。 形成接触蚀刻停止层以覆盖层叠结构和基板。 在衬底上形成材料层并暴露覆盖层叠结构的接触蚀刻停止层的顶部。 顶部被纠正。
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公开(公告)号：US20130307084A1
公开(公告)日：2013-11-21
申请号：US13949230
申请日：2013-07-24
发明人： Chun-Mao Chiou , Ti-Bin Chen , Tsung-Min Kuo , Shyan-Liang Chou , Yao-Chang Wang , Chi-Sheng Tseng , Jie-Ning Yang , Po-Jui Liao
IPC分类号： H01L27/06
CPC分类号： H01L27/0629
摘要： A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.
摘要翻译： 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。
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公开(公告)号：US08692334B2
公开(公告)日：2014-04-08
申请号：US13949230
申请日：2013-07-24
发明人： Chun-Mao Chiou , Ti-Bin Chen , Tsung-Min Kuo , Shyan-Liang Chou , Yao-Chang Wang , Chi-Sheng Tseng , Jie-Ning Yang , Po-Jui Liao
IPC分类号： H01L21/70
CPC分类号： H01L27/0629
摘要： A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.
摘要翻译： 一种制造与具有金属栅极的晶体管集成的电阻器的方法包括提供具有晶体管区域和限定在其上的电阻器区域的衬底，晶体管位于晶体管区域中，并且电阻器位于电阻器区域中; 形成暴露所述晶体管顶部和所述基板上的所述电阻器的电介质层; 执行第一蚀刻工艺以去除电阻器的部分以分别在电阻器的两个相对端处形成两个第一沟槽; 在所述电阻器区域中形成图案化保护层; 执行第二蚀刻工艺以去除晶体管的伪栅极以在晶体管区域中形成第二沟槽; 以及形成填充所述第一沟槽和所述第二沟槽的金属层。
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公开(公告)号：US20140242770A1
公开(公告)日：2014-08-28
申请号：US13773635
申请日：2013-02-22
发明人： Kuang-Hung Huang , Jie-Ning Yang , Yao-Chang Wang , Chi-Sheng Tseng , Po-Jui Liao , Shih-Chang Chang
IPC分类号： H01L29/66
CPC分类号： H01L29/66545 , H01L21/76801 , H01L21/76834 , H01L29/4966 , H01L29/517 , H01L29/6653
摘要： A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.
摘要翻译： 半导体工艺包括以下步骤。 在基板上形成层叠结构。 形成接触蚀刻停止层以覆盖层叠结构和基板。 在衬底上形成材料层并暴露覆盖层叠结构的接触蚀刻停止层的顶部。 顶部被纠正。
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