公开(公告)号：US20160260613A1

公开(公告)日：2016-09-08

申请号：US15155064

申请日：2016-05-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Tsung-Hung Chang ,  I-Ming Tseng

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/26513 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/31116 ,  H01L21/32155 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

Abstract: The present invention provides a semiconductor structure, comprising at least two gate electrodes disposed on a substrate, wherein each gate electrode is mushroom-shaped and respectively has a salicide region on a top of the gate electrode, wherein the width of the salicide region is larger than the width of the gate electrode. A recess is disposed between each gate electrode, wherein the recess has a recess extension disposed under the salicide region. A spacer fills the extension of the recess, wherein the profile of each gate electrode is a tapered surface, and a contact etching stop layer (CESL) covers the gate electrodes.

Abstract translation: 本发明提供一种半导体结构，其包括设置在基板上的至少两个栅电极，其中每个栅电极是蘑菇状的，并且在栅电极的顶部上分别具有自对准硅化物区域，其中自对准区域的宽度较大 比栅电极的宽度大。 在每个栅电极之间设置凹部，其中凹部具有设置在自对准区域下方的凹陷延伸部。 间隔件填充凹部的延伸部，其中每个栅电极的轮廓是锥形表面，并且接触蚀刻停止层（CESL）覆盖栅电极。

公开(公告)号：US20160013104A1

公开(公告)日：2016-01-14

申请号：US14455939

申请日：2014-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L21/768 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/665 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个金属栅极的衬底，与所述至少一个金属栅极的两侧相邻的源极/漏极区域以及围绕所述至少一个金属栅极的层间电介质层 ; 在所述ILD层中形成多个接触孔以暴露所述源/漏区; 在所述接触孔中形成第一金属层; 执行第一热处理过程; 并执行第二热处理过程。

公开(公告)号：US20130288446A1

公开(公告)日：2013-10-31

申请号：US13928366

申请日：2013-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Ling-Chun Chou ,  Tsung-Hung Chang ,  Chun-Yuan Wu

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7847

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract translation: 公开了一种包括衬底和设置在衬底上的栅极结构的半导体结构。 栅极结构包括设置在基板上的栅极介质层，设置在栅极介电层上的栅极材料层和具有矩形横截面的外部间隔物。 外隔离物的顶表面比栅极材料层的顶表面低。

公开(公告)号：US09984974B1

公开(公告)日：2018-05-29

申请号：US15863986

申请日：2018-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L21/338 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/06 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.

公开(公告)号：US09899322B2

公开(公告)日：2018-02-20

申请号：US15257921

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L21/338 ,  H01L23/528 ,  H01L21/768 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

公开(公告)号：US09324610B2

公开(公告)日：2016-04-26

申请号：US14455939

申请日：2014-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/665 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个金属栅极的衬底，与所述至少一个金属栅极的两侧相邻的源极/漏极区域以及围绕所述至少一个金属栅极的层间电介质层 ; 在所述ILD层中形成多个接触孔以暴露所述源/漏区; 在所述接触孔中形成第一金属层; 执行第一热处理过程; 并执行第二热处理过程。

公开(公告)号：US20160071800A1

公开(公告)日：2016-03-10

申请号：US14513230

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia Chang Hsu ,  Hsin-Fu Huang ,  Chun-Yuan Wu ,  Shih-Fang Tzou

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.

Abstract translation: 提供了包括电介质层，钛层，氮化钛层和金属的半导体结构。 电介质层设置在基板上，其中介电层具有通孔。 钛层覆盖通孔，其中钛层具有低于1500Mpa的拉伸应力。 氮化钛层共形地覆盖钛层。 金属填充通孔。 本发明还提供了一种用于形成所述半导体结构的半导体工艺。 半导体工艺包括以下步骤。 介电层形成在基板上，其中电介质具有通孔。 钛层保形地覆盖通孔，其中钛层具有低于500Mpa的压应力。 形成氮化钛层以保形地覆盖钛层。 金属填充通孔。

公开(公告)号：US09564371B2

公开(公告)日：2017-02-07

申请号：US14514374

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Jia-Rong Wu ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823431

Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

Abstract translation: 一种半导体器件的制造方法，其特征在于，首先，在基板上形成有基板，在所述散热片结构上形成有多个栅极结构，然后将硬掩模层和第一光致抗蚀剂层 形成在鳍结构上，然后在第一光致抗蚀剂层上进行第一蚀刻工艺，然后在剩余的第一光致抗蚀剂层和剩余的硬掩模层上形成多个图案化的光致抗蚀剂层，其中每个图案化的光致抗蚀剂层被设置 每个栅极结构的正上方，并且每个图案化的光致抗蚀剂的宽度大于每个栅极结构的宽度，并且图案化的光致抗蚀剂层用作硬掩模以执行第二蚀刻工艺以形成多个第二沟槽。

公开(公告)号：US20160064327A1

公开(公告)日：2016-03-03

申请号：US14494607

申请日：2014-09-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 基板上的第一金属栅极; 第一个金属门上的第一个硬掩模; 在第一金属栅极的顶部和周围的层间绝缘层（ILD）层; 以及嵌入ILD层中的图案化金属层，其中图案化金属层的顶表面比第一硬掩模的顶表面低。

公开(公告)号：US09105651B2

公开(公告)日：2015-08-11

申请号：US13940103

申请日：2013-07-11

Applicant: United Microelectronics Corp.

Inventor： Tsung-Hung Chang ,  Yi-Wei Chen ,  I-Fang Huang

IPC: H01L21/00 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

Abstract: Provided is a method of fabricating a MOS device including the following steps. A gate structure is formed on a substrate and a first spacer is formed at a sidewall of the gate structure. A first implant process is performed to form source and drain extension regions in the substrate. A spacer material layer is formed on the gate structure, the first spacer and the substrate. A treatment process is performed so that stress from the spacer material layer is applied onto and memorized in a channel between two source and drain extension regions. An anisotropic process is performed to remove a portion of the spacer material so that a second spacer is formed. A second implant process is performed to form source and drain regions in the substrate.

Abstract translation: 提供了一种制造MOS器件的方法，包括以下步骤。 栅极结构形成在衬底上，并且第一间隔物形成在栅极结构的侧壁处。 执行第一注入工艺以在衬底中形成源极和漏极延伸区域。 在栅极结构，第一间隔物和衬底上形成间隔物层。 执行处理过程，使得来自间隔物材料层的应力施加到并存储在两个源极和漏极延伸区域之间的沟道中。 执行各向异性处理以去除间隔物材料的一部分，从而形成第二间隔物。 执行第二注入工艺以在衬底中形成源区和漏区。