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    Hard mask removal
    1.
    发明申请
    Hard mask removal 有权
    硬面膜去除

    公开(公告)号：US20050006347A1

    公开(公告)日：2005-01-13

    申请号：US10615558

    申请日：2003-07-08

    申请人： Venkatesh Gopinath ,  Arvind Kamath ,  Mohammad Mirabedini ,  Ming-Yi Lee ,  Brian Baylis

    发明人： Venkatesh Gopinath ,  Arvind Kamath ,  Mohammad Mirabedini ,  Ming-Yi Lee ,  Brian Baylis

    IPC分类号： H01L21/311 ,  C23F1/00

    CPC分类号： H01L21/31144 ,  H01L21/31116

    摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.

    摘要翻译： 从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层 以去除硬掩模层，而不会有害地蚀刻下面的层。 修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。 图案化硬掩模层。 蚀刻图案层以暴露下层的部分。 硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的 掩模层。

    Polysilicon gate salicidation
    2.
    发明授权
    Polysilicon gate salicidation 有权
    多晶硅栅盐化

    公开(公告)号：US06544829B1

    公开(公告)日：2003-04-08

    申请号：US10251016

    申请日：2002-09-20

    申请人： Venkatesh Gopinath ,  Mohammad Mirabedini ,  Charles E. May ,  Arvind Kamath

    发明人： Venkatesh Gopinath ,  Mohammad Mirabedini ,  Charles E. May ,  Arvind Kamath

    IPC分类号： H01L218238

    CPC分类号： H01L21/823835 ,  H01L21/823814 ,  H01L21/823878

    摘要： A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region. The exposed second portions of the unpatterned polysilicon layer are removed to define polysilicon gate electrode precursors under the gate electrode masks. The gate electrode masks are removed from the polysilicon gate electrode precursors, and a metal layer is deposited over the polysilicon gate electrode precursors and the source drain regions. The integrated circuit substrate is annealed to substantially completely consume the polysilicon gate electrode precursors and form silicide gate electrodes from the polysilicon gate electrode precursors and the overlying metal layer, by which silicide contacts in the source drain regions are also formed.

    摘要翻译： 一种在CMOS工艺流程中制造基本上完全硅化的多晶硅栅电极的方法。 在集成电路基板上形成硬掩模材料，其中集成电路基板包括覆盖在栅极氧化物层上的未图案化的多晶硅层和设置在隔离结构之间的阱区域。 去除硬掩模材料的部分以限定覆盖未图案化多晶硅层和栅极氧化物层的第一部分的栅电极掩模，留下未图案化的多晶硅层和栅极氧化物层的暴露的第二部分。 集成电路基板暴露于穿过栅极氧化物层的第二部分但不穿过限定阱区中的源极漏极区域的栅极电极掩模之下的栅极氧化物层的第一部分的掺杂剂。 去除未图案化的多晶硅层的暴露的第二部分以在栅极电极掩模下限定多晶硅栅电极前体。 栅极电极掩模从多晶硅栅电极前驱体去除，并且金属层沉积在多晶硅栅极电极前体和源极漏极区上。 将集成电路基板退火以基本上完​​全消耗多晶硅栅极电极前体，并从多晶硅栅极电极前体和上覆金属层形成硅化物栅极电极，由此源极漏极区域中的硅化物接触也形成。

    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit
    3.
    发明授权
    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit 有权

    公开(公告)号：US06562729B2

    公开(公告)日：2003-05-13

    申请号：US10171700

    申请日：2002-06-14

    申请人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    发明人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    IPC分类号： H01L2131

    CPC分类号： H01L21/823462

    摘要： Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit
    4.
    发明授权
    Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit 有权

    公开(公告)号：US06436845B1

    公开(公告)日：2002-08-20

    申请号：US09723516

    申请日：2000-11-28

    申请人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    发明人： Arvind Kamath ,  Rajiv Patel ,  Mohammad Mirabedini

    IPC分类号： H01L2131

    CPC分类号： H01L21/823462

    摘要： Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

    Method for implanting ions in a semiconductor
    8.
    发明授权
    Method for implanting ions in a semiconductor 有权
    在半导体中注入离子的方法

    公开(公告)号：US07148131B1

    公开(公告)日：2006-12-12

    申请号：US10226884

    申请日：2002-08-23

    申请人： Agajan Suvkhanov ,  Mohammad Mirabedini

    发明人： Agajan Suvkhanov ,  Mohammad Mirabedini

    IPC分类号： H01L21/425

    CPC分类号： H01L29/66537 ,  H01L21/26513 ,  H01L21/324 ,  Y10S438/914

    摘要： A method for implanting ions in a semiconductor is disclosed. The method includes implanting indium ions into a substrate of a semiconductor material of the semiconductor device for a first time period. The method also includes implanting boron ions into the substrate for a second time period, wherein the first time period is initiated prior to the second time period.

    摘要翻译： 公开了一种在半导体中注入离子的方法。 该方法包括在第一时间段内将铟离子注入到半导体器件的半导体材料的衬底中。 该方法还包括在第二时间段内将硼离子注入衬底中，其中第一时间段在第二时间段之前启动。

    Ion recoil implantation and enhanced carrier mobility in CMOS device
    9.
    发明申请
    Ion recoil implantation and enhanced carrier mobility in CMOS device 有权
    离子反冲注入和CMOS器件中增强的载流子迁移率

    公开(公告)号：US20050167654A1

    公开(公告)日：2005-08-04

    申请号：US11098290

    申请日：2005-04-04

    申请人： Agajan Suvkhanov ,  Mohammad Mirabedini

    发明人： Agajan Suvkhanov ,  Mohammad Mirabedini

    IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/10 ,  H01L31/109

    CPC分类号： H01L21/823864 ,  H01L21/26506 ,  H01L21/26526 ,  H01L21/823807 ,  H01L29/1054

    摘要： An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.

    摘要翻译： 集成电路（IC）包括在其上具有离子的半导体衬底之上形成的CMOS器件，其通过离子反冲程序注入到半导体衬底中。 IC优选但不一定在CMOS器件中并入次0.1微米技术。 注入的离子可以优选为锗离子。 应变硅层优选但不一定形成在半导体衬底的离子注入层的上方。 应变硅层可以通过在离子注入层上的硅外延生长或通过使离子以这样的能量回到半导体衬底中形成，使得其表面附近的半导体衬底的区域基本上保持 没有离子，从而在基本上无离子的区域中形成应变硅层。